A channel-sharable built-in self-test scheme for multi-channel DRAMs

Kuan Te Wu, Jin Fu Li, Chih Yen Lo, Jenn Shiang Lai, Ding Ming Kwai, Yung Fa Chou

研究成果: 書貢獻/報告類型會議論文篇章同行評審

1 引文 斯高帕斯(Scopus)

摘要

Various multi-channel dynamic random access memories (MC-DRAMs) have been proposed for the demand of high bandwidth. In this paper, we propose a channel-sharable built-in self-test (BIST) scheme for MC-DRAMs. The BIST can apply test patterns and evaluate test responses for multiple channels simultaneously regardless of the difference of the read/write latency among the channels. Therefore, the proposed BIST can reduce the test time. In our simulation cases show that the proposed BIST scheme can achieve about 11% test time reduction in comparison with an existing conventional shared BIST scheme for a two-channel 1G-bit DRAM by consuming about 0.003% additional area cost.

原文???core.languages.en_GB???
主出版物標題ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
頁面245-250
頁數6
ISBN(電子)9781509006021
DOIs
出版狀態已出版 - 20 2月 2018
事件23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of
持續時間: 22 1月 201825 1月 2018

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2018-January

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???event.eventtypes.event.conference???23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
國家/地區Korea, Republic of
城市Jeju
期間22/01/1825/01/18

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