A channel-sharable built-in self-test scheme for multi-channel DRAMs

Kuan Te Wu; Jin Fu Li; Chih Yen Lo; Jenn Shiang Lai; Ding Ming Kwai; Yung Fa Chou

doi:10.1109/ASPDAC.2018.8297313

A channel-sharable built-in self-test scheme for multi-channel DRAMs

Kuan Te Wu, Jin Fu Li, Chih Yen Lo, Jenn Shiang Lai, Ding Ming Kwai, Yung Fa Chou

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

Various multi-channel dynamic random access memories (MC-DRAMs) have been proposed for the demand of high bandwidth. In this paper, we propose a channel-sharable built-in self-test (BIST) scheme for MC-DRAMs. The BIST can apply test patterns and evaluate test responses for multiple channels simultaneously regardless of the difference of the read/write latency among the channels. Therefore, the proposed BIST can reduce the test time. In our simulation cases show that the proposed BIST scheme can achieve about 11% test time reduction in comparison with an existing conventional shared BIST scheme for a two-channel 1G-bit DRAM by consuming about 0.003% additional area cost.

原文	???core.languages.en_GB???
主出版物標題	ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	245-250
頁數	6
ISBN（電子）	9781509006021
DOIs	https://doi.org/10.1109/ASPDAC.2018.8297313
出版狀態	已出版 - 20 2月 2018
事件	23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of 持續時間: 22 1月 2018 → 25 1月 2018

出版系列

名字	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
卷	2018-January

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
國家/地區	Korea, Republic of
城市	Jeju
期間	22/01/18 → 25/01/18

存取文件

10.1109/ASPDAC.2018.8297313

堆疊式記憶體測試與可靠度增強技術(2/3)
Li, J.-F. (PI)
1/08/17 → 31/07/18
研究計畫: Research
應用於物聯網之新興非揮發性記憶體測試技術(2/3)
Li, J.-F. (PI)
1/08/17 → 31/07/18
研究計畫: Research

引用此

Wu, K. T., Li, J. F., Lo, C. Y., Lai, J. S., Kwai, D. M., & Chou, Y. F. (2018). A channel-sharable built-in self-test scheme for multi-channel DRAMs. 於 ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings (頁 245-250). (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 卷 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2018.8297313

@inproceedings{114c4a3047f44f119814bc44501973db,

title = "A channel-sharable built-in self-test scheme for multi-channel DRAMs",

abstract = "Various multi-channel dynamic random access memories (MC-DRAMs) have been proposed for the demand of high bandwidth. In this paper, we propose a channel-sharable built-in self-test (BIST) scheme for MC-DRAMs. The BIST can apply test patterns and evaluate test responses for multiple channels simultaneously regardless of the difference of the read/write latency among the channels. Therefore, the proposed BIST can reduce the test time. In our simulation cases show that the proposed BIST scheme can achieve about 11% test time reduction in comparison with an existing conventional shared BIST scheme for a two-channel 1G-bit DRAM by consuming about 0.003% additional area cost.",

keywords = "DRAM, March test, built-in self-test, channel-based DRAM, test",

author = "Wu, {Kuan Te} and Li, {Jin Fu} and Lo, {Chih Yen} and Lai, {Jenn Shiang} and Kwai, {Ding Ming} and Chou, {Yung Fa}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 ; Conference date: 22-01-2018 Through 25-01-2018",

year = "2018",

month = feb,

day = "20",

doi = "10.1109/ASPDAC.2018.8297313",

language = "???core.languages.en_GB???",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "245--250",

booktitle = "ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings",

}

Wu, KT, Li, JF, Lo, CY, Lai, JS, Kwai, DM & Chou, YF 2018, A channel-sharable built-in self-test scheme for multi-channel DRAMs. 於 ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 卷 2018-January, Institute of Electrical and Electronics Engineers Inc., 頁 245-250, 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea, Republic of, 22/01/18. https://doi.org/10.1109/ASPDAC.2018.8297313

A channel-sharable built-in self-test scheme for multi-channel DRAMs. / Wu, Kuan Te; Li, Jin Fu; Lo, Chih Yen 等.
ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 245-250 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 卷 2018-January).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

TY - GEN

T1 - A channel-sharable built-in self-test scheme for multi-channel DRAMs

AU - Wu, Kuan Te

AU - Li, Jin Fu

AU - Lo, Chih Yen

AU - Lai, Jenn Shiang

AU - Kwai, Ding Ming

AU - Chou, Yung Fa

PY - 2018/2/20

Y1 - 2018/2/20

N2 - Various multi-channel dynamic random access memories (MC-DRAMs) have been proposed for the demand of high bandwidth. In this paper, we propose a channel-sharable built-in self-test (BIST) scheme for MC-DRAMs. The BIST can apply test patterns and evaluate test responses for multiple channels simultaneously regardless of the difference of the read/write latency among the channels. Therefore, the proposed BIST can reduce the test time. In our simulation cases show that the proposed BIST scheme can achieve about 11% test time reduction in comparison with an existing conventional shared BIST scheme for a two-channel 1G-bit DRAM by consuming about 0.003% additional area cost.

AB - Various multi-channel dynamic random access memories (MC-DRAMs) have been proposed for the demand of high bandwidth. In this paper, we propose a channel-sharable built-in self-test (BIST) scheme for MC-DRAMs. The BIST can apply test patterns and evaluate test responses for multiple channels simultaneously regardless of the difference of the read/write latency among the channels. Therefore, the proposed BIST can reduce the test time. In our simulation cases show that the proposed BIST scheme can achieve about 11% test time reduction in comparison with an existing conventional shared BIST scheme for a two-channel 1G-bit DRAM by consuming about 0.003% additional area cost.

KW - DRAM

KW - March test

KW - built-in self-test

KW - channel-based DRAM

KW - test

UR - http://www.scopus.com/inward/record.url?scp=85045334641&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2018.8297313

DO - 10.1109/ASPDAC.2018.8297313

M3 - 會議論文篇章

AN - SCOPUS:85045334641

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 245

EP - 250

BT - ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018

Y2 - 22 January 2018 through 25 January 2018

ER -

Wu KT, Li JF, Lo CY, Lai JS, Kwai DM, Chou YF. A channel-sharable built-in self-test scheme for multi-channel DRAMs. 於 ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 245-250. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2018.8297313

A channel-sharable built-in self-test scheme for multi-channel DRAMs

摘要

出版系列

???event.eventtypes.event.conference???

存取文件

指紋

專案

堆疊式記憶體測試與可靠度增強技術(2/3)

應用於物聯網之新興非揮發性記憶體測試技術(2/3)

引用此