A Built-in Spice Time-domain Variation Model of the BTI-induced Random Trap Fluctuation (RTF) in 14 nm FinFETs

L. C. Lin, Z. Y. Wang, M. Y. Lee, J. K. Chang, E. R. Hsieh, J. C. Guo, Steve S. Chung

研究成果: 書貢獻/報告類型會議論文篇章同行評審

摘要

In the advanced FinFET technology, variability has been one of the main scaling concerns. The undesirable variation sources will be finally reflected in real circuit operation. In this paper, a carrier transport mechanism based on Virtual Source Model was first developed. Then, the BTI-induced degradation of device performance after long time operation is discussed. The technique of Random Trap Profiling is used to profile the lateral trap density in the channel from the source to drain. Then, a variation model from the level of device to circuit was built by Virtual Source Model. Finally, the model was implemented in Spice which can simulate the behavior of basic logic gate.

原文???core.languages.en_GB???
主出版物標題2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781665459792
DOIs
出版狀態已出版 - 2022
事件2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022 - Honolulu, United States
持續時間: 11 6月 202212 6月 2022

出版系列

名字2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022

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???event.eventtypes.event.conference???2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022
國家/地區United States
城市Honolulu
期間11/06/2212/06/22

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