A built-in self-test scheme with diagnostics support for embedded SRAM

Chih Wea Wang, Chi Feng Wu, Jin Fu Li, Cheng Wen Wu, Tony Teng, Kevin Chiu, Hsiao Ping Lin

研究成果: 雜誌貢獻期刊論文同行評審

1 引文 斯高帕斯(Scopus)


In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.

頁(從 - 到)637-647
期刊Journal of Electronic Testing: Theory and Applications (JETTA)
出版狀態已出版 - 12月 2002


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