A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs

Wei Hsuan Yang, Jin Fu Li, Chun Lung Hsu, Chi Tien Sun, Shih Hsu Huang

研究成果: 書貢獻/報告類型會議論文篇章同行評審

摘要

Three-dimensional (3D) dynamic random access memory (DRAM) using through-silicon-via (TSV) has been proposed to overcome the memory wall. WideIO DRAM is one type of 3D DRAMs. IOs of a WideIO DRAM die are wrapped by a 1149. 1-like boundary scan controlled by a scan controller. In this paper, we propose a built-in-self-Test (BIST) scheme for the post-bond testing of TSVs of a logic-DRAM stack. The BIST circuit implemented in the logic die can generate control signals for the scan controller and test patterns for the testing of TSVs.

原文???core.languages.en_GB???
主出版物標題IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728148700
DOIs
出版狀態已出版 - 10月 2019
事件2019 IEEE International 3D Systems Integration Conference, 3DIC 2019 - Sendai, Japan
持續時間: 8 10月 201910 10月 2019

出版系列

名字IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???2019 IEEE International 3D Systems Integration Conference, 3DIC 2019
國家/地區Japan
城市Sendai
期間8/10/1910/10/19

指紋

深入研究「A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs」主題。共同形成了獨特的指紋。

引用此