A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs

Wei Hsuan Yang; Jin Fu Li; Chun Lung Hsu; Chi Tien Sun; Shih Hsu Huang

doi:10.1109/3DIC48104.2019.9058898

A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs

Wei Hsuan Yang, Jin Fu Li, Chun Lung Hsu, Chi Tien Sun, Shih Hsu Huang

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

Three-dimensional (3D) dynamic random access memory (DRAM) using through-silicon-via (TSV) has been proposed to overcome the memory wall. WideIO DRAM is one type of 3D DRAMs. IOs of a WideIO DRAM die are wrapped by a 1149. 1-like boundary scan controlled by a scan controller. In this paper, we propose a built-in-self-Test (BIST) scheme for the post-bond testing of TSVs of a logic-DRAM stack. The BIST circuit implemented in the logic die can generate control signals for the scan controller and test patterns for the testing of TSVs.

原文	???core.languages.en_GB???
主出版物標題	IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781728148700
DOIs	https://doi.org/10.1109/3DIC48104.2019.9058898
出版狀態	已出版 - 10月 2019
事件	2019 IEEE International 3D Systems Integration Conference, 3DIC 2019 - Sendai, Japan 持續時間: 8 10月 2019 → 10 10月 2019

出版系列

名字	IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	2019 IEEE International 3D Systems Integration Conference, 3DIC 2019
國家/地區	Japan
城市	Sendai
期間	8/10/19 → 10/10/19

存取文件

10.1109/3DIC48104.2019.9058898

深度神經網路系統之強健性與可靠性增強技術(1/3)
Li, J.-F. (PI)
1/08/19 → 31/07/20
研究計畫: Research

引用此

Yang, W. H., Li, J. F., Hsu, C. L., Sun, C. T., & Huang, S. H. (2019). A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. 於 IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019 文章 9058898 (IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/3DIC48104.2019.9058898

@inproceedings{8a579058e4a0474bb0cfa32f904db068,

title = "A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs",

abstract = "Three-dimensional (3D) dynamic random access memory (DRAM) using through-silicon-via (TSV) has been proposed to overcome the memory wall. WideIO DRAM is one type of 3D DRAMs. IOs of a WideIO DRAM die are wrapped by a 1149. 1-like boundary scan controlled by a scan controller. In this paper, we propose a built-in-self-Test (BIST) scheme for the post-bond testing of TSVs of a logic-DRAM stack. The BIST circuit implemented in the logic die can generate control signals for the scan controller and test patterns for the testing of TSVs.",

keywords = "3D IC, built-in self-Test, DRAM die, TSV",

author = "Yang, {Wei Hsuan} and Li, {Jin Fu} and Hsu, {Chun Lung} and Sun, {Chi Tien} and Huang, {Shih Hsu}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE International 3D Systems Integration Conference, 3DIC 2019 ; Conference date: 08-10-2019 Through 10-10-2019",

year = "2019",

month = oct,

doi = "10.1109/3DIC48104.2019.9058898",

language = "???core.languages.en_GB???",

series = "IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019",

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Yang, WH, Li, JF , Hsu, CL, Sun, CT & Huang, SH 2019, A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. 於 IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019., 9058898, IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International 3D Systems Integration Conference, 3DIC 2019, Sendai, Japan, 8/10/19. https://doi.org/10.1109/3DIC48104.2019.9058898

A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. / Yang, Wei Hsuan; Li, Jin Fu ; Hsu, Chun Lung 等.
IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 9058898 (IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

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T1 - A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs

AU - Yang, Wei Hsuan

AU - Li, Jin Fu

AU - Hsu, Chun Lung

AU - Sun, Chi Tien

AU - Huang, Shih Hsu

PY - 2019/10

Y1 - 2019/10

N2 - Three-dimensional (3D) dynamic random access memory (DRAM) using through-silicon-via (TSV) has been proposed to overcome the memory wall. WideIO DRAM is one type of 3D DRAMs. IOs of a WideIO DRAM die are wrapped by a 1149. 1-like boundary scan controlled by a scan controller. In this paper, we propose a built-in-self-Test (BIST) scheme for the post-bond testing of TSVs of a logic-DRAM stack. The BIST circuit implemented in the logic die can generate control signals for the scan controller and test patterns for the testing of TSVs.

AB - Three-dimensional (3D) dynamic random access memory (DRAM) using through-silicon-via (TSV) has been proposed to overcome the memory wall. WideIO DRAM is one type of 3D DRAMs. IOs of a WideIO DRAM die are wrapped by a 1149. 1-like boundary scan controlled by a scan controller. In this paper, we propose a built-in-self-Test (BIST) scheme for the post-bond testing of TSVs of a logic-DRAM stack. The BIST circuit implemented in the logic die can generate control signals for the scan controller and test patterns for the testing of TSVs.

KW - 3D IC

KW - built-in self-Test

KW - DRAM die

KW - TSV

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PB - Institute of Electrical and Electronics Engineers Inc.

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A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs

摘要

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專案

深度神經網路系統之強健性與可靠性增強技術(1/3)

引用此