A built-in self-test scheme for the post-bond test of TSVs in 3D ICs

Keyphrases

• Built-in-self-test (BiST) 100%
• Three-Dimensional ICs 100%
• Post-bond Test 100%
• Test Circuit 83%
• Through Silicon via 66%
• Area Cost 33%
• 3D IC 33%
• Via Arrays 33%
• IEEE 1500 16%
• CMOS Technology 16%
• Area Overhead 16%
• Test Time Reduction 16%
• Stuck-at 16%
• Cell Size 16%
• Integrated Circuit Technology 16%
• Test Diagnostics 16%
• Three-dimensional Integration 16%
• Low Silicon 16%
• Silicon Area 16%
• Delayed Diagnosis 16%

Engineering

• Built-in Self Test 100%
• Test Circuit 83%
• Three Dimensional Integrated Circuits 33%
• Simulation Result 16%
• Test Time 16%
• Clock Cycle 16%
• Area Overhead 16%
• Integrated Circuit 16%