A built-in self-repair scheme for multiport RAMs

Tsu Wei Tseng, Chun Hsien Wu, Yu Jen Huang, Jin Fu Li, Alex Pao, Kevin Chiu, Eliot Chen

研究成果: 書貢獻/報告類型會議論文篇章同行評審

23 引文 斯高帕斯(Scopus)


Built-in self-repair (BISR) techniques have been widely used for enhancing the yield of embedded memories. This paper presents an efficient BISR scheme for multiport RAMs (MPRAMs). The BISR scheme has a defect-location module (DLM) executing a defect-location algorithm to locate inter-port defects. This enhances the fault-location capability of the applied test algorithm with only a few amount of cost of testing time. A built-in redundancy analyzer (BIRA) executing a proposed redundancy analysis algorithm is also proposed to allocate two-dimension redundancy of MPRAMs. Experimental results show that if a faulty MPRAM has 20% inter-port faults, the DLM can boost the increment of repair rate from 8.4% to 14.4% for different redundancy configurations. The area cost of the BIRA and DLM is small, it is only about 1% for a 4096 × 128-bit MPRAM with 1 spare row and 1 spare IO.

主出版物標題Proceedings - 25th IEEE VLSI Test Symposium, VTS'07
出版狀態已出版 - 2007
事件25th IEEE VLSI Test Symposium, VTS'07 - Berkeley, CA, United States
持續時間: 6 5月 200710 5月 2007


名字Proceedings of the IEEE VLSI Test Symposium


???event.eventtypes.event.conference???25th IEEE VLSI Test Symposium, VTS'07
國家/地區United States
城市Berkeley, CA


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