A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

Chih Sheng Hou; Yong Xiao Chen; Jin Fu Li; Chih Yen Lo; Ding Ming Kwai; Yung Fa Chou

doi:10.1109/TEST.2016.7805832

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

Chih Sheng Hou, Yong Xiao Chen, Jin Fu Li, Chih Yen Lo, Ding Ming Kwai, Yung Fa Chou

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

10 引文斯高帕斯（Scopus）

摘要

With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.

原文	???core.languages.en_GB???
主出版物標題	Proceedings - 2016 IEEE International Test Conference, ITC 2016
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781467387736
DOIs	https://doi.org/10.1109/TEST.2016.7805832
出版狀態	已出版 - 2 7月 2016
事件	47th IEEE International Test Conference, ITC 2016 - Fort Worth, United States 持續時間: 15 11月 2016 → 17 11月 2016

出版系列

名字	Proceedings - International Test Conference
卷	0
ISSN（列印）	1089-3539

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	47th IEEE International Test Conference, ITC 2016
國家/地區	United States
城市	Fort Worth
期間	15/11/16 → 17/11/16

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10.1109/TEST.2016.7805832

應用於三維積體電路可測性及可靠性設計技術-總計畫暨子計畫一：三維積體電路中堆疊式記憶體與晶粒間連接線可測性與可靠性技術
Li, J.
1/05/15 → 31/07/16
研究計畫: Research

引用此

Hou, C. S., Chen, Y. X., Li, J. F., Lo, C. Y., Kwai, D. M., & Chou, Y. F. (2016). A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. 於 Proceedings - 2016 IEEE International Test Conference, ITC 2016 [7805832] (Proceedings - International Test Conference; 卷 0). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TEST.2016.7805832

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title = "A built-in self-repair scheme for DRAMs with spare rows, columns, and bits",

abstract = "With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.",

keywords = "built-in self-repair, built-in self-Test, DRAM, redundancy, redundancy analysis",

author = "Hou, {Chih Sheng} and Chen, {Yong Xiao} and Li, {Jin Fu} and Lo, {Chih Yen} and Kwai, {Ding Ming} and Chou, {Yung Fa}",

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Hou, CS, Chen, YX, Li, JF, Lo, CY, Kwai, DM & Chou, YF 2016, A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. 於 Proceedings - 2016 IEEE International Test Conference, ITC 2016., 7805832, Proceedings - International Test Conference, 卷 0, Institute of Electrical and Electronics Engineers Inc., 47th IEEE International Test Conference, ITC 2016, Fort Worth, United States, 15/11/16. https://doi.org/10.1109/TEST.2016.7805832

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. / Hou, Chih Sheng; Chen, Yong Xiao; Li, Jin Fu 等.

Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7805832 (Proceedings - International Test Conference; 卷 0).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

TY - GEN

T1 - A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

AU - Hou, Chih Sheng

AU - Chen, Yong Xiao

AU - Li, Jin Fu

AU - Lo, Chih Yen

AU - Kwai, Ding Ming

AU - Chou, Yung Fa

PY - 2016/7/2

Y1 - 2016/7/2

N2 - With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.

AB - With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.

KW - built-in self-repair

KW - built-in self-Test

KW - DRAM

KW - redundancy

KW - redundancy analysis

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T3 - Proceedings - International Test Conference

BT - Proceedings - 2016 IEEE International Test Conference, ITC 2016

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 15 November 2016 through 17 November 2016

ER -

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

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專案

應用於三維積體電路可測性及可靠性設計技術-總計畫暨子計畫一：三維積體電路中堆疊式記憶體與晶粒間連接線可測性與可靠性技術

引用此