A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

Chih Sheng Hou, Yong Xiao Chen, Jin Fu Li, Chih Yen Lo, Ding Ming Kwai, Yung Fa Chou

研究成果: 書貢獻/報告類型會議論文篇章同行評審

13 引文 斯高帕斯(Scopus)

摘要

With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.

原文???core.languages.en_GB???
主出版物標題Proceedings - 2016 IEEE International Test Conference, ITC 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781467387736
DOIs
出版狀態已出版 - 2 7月 2016
事件47th IEEE International Test Conference, ITC 2016 - Fort Worth, United States
持續時間: 15 11月 201617 11月 2016

出版系列

名字Proceedings - International Test Conference
0
ISSN(列印)1089-3539

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???event.eventtypes.event.conference???47th IEEE International Test Conference, ITC 2016
國家/地區United States
城市Fort Worth
期間15/11/1617/11/16

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