A built-in self-repair scheme for 3-D RAMs with interdie redundancy

Che Wei Chou; Yu Jen Huang; Jin Fu Li

doi:10.1109/TCAD.2012.2222882

A built-in self-repair scheme for 3-D RAMs with interdie redundancy

Che Wei Chou, Yu Jen Huang, Jin Fu Li

電機工程學系

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

11 引文斯高帕斯（Scopus）

摘要

3-D integration using through silicon via is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for the application of 3-D integration technology. However, yield will be a key challenge for the volume production of 3-D RAMs. In this paper, we present yield-enhancement techniques for 3-D RAMs. An interdie redundancy scheme is proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to different bonding technologies for 3-D RAMs with interdie redundancy are proposed as well. Finally, a built-in self-repair (BISR) scheme is proposed to perform the repair of 3-D RAMs with interdie redundancies. The BISR circuits in two stacked dies can work together to allocate interdie redundancies. Simulation results show that the proposed yield-enhancement techniques can effectively improve the yield of 3-D RAMs.

原文	???core.languages.en_GB???
文章編號	6480861
頁（從 - 到）	572-583
頁數	12
期刊	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
卷	32
發行號	4
DOIs	https://doi.org/10.1109/TCAD.2012.2222882
出版狀態	已出版 - 2013

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10.1109/TCAD.2012.2222882

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A built-in self-repair scheme for 3-D RAMs with interdie redundancy

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