A built-in redundancy-analysis scheme for RAMs with 2D redundancy using ID local bitmap

Tsu Wei Tseng, Jin Fu Li, Da Ming Chang

研究成果: 書貢獻/報告類型會議論文篇章同行評審

20 引文 斯高帕斯(Scopus)

摘要

Built-in self-repair (BISR) technique is gaining popular for repairing embedded memory cores in system-on-chips (SOCs). To increase the utilization of memory redundancy, the BISR technique usually needs to perform built-in redundancy-analysis (BIRA) algorithm for redundancy allocation. This paper presents an effcient BIRA scheme for embedded memory repair. The BIRA scheme executes the 2D redundancy allocation based on the ID local bitmap. This enables that the BIRA circuitry can be implemented with low area cost. Also, the BIRA algorithm can provide good repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories). Experimental results show that the repair rate of the proposed BIRA scheme approximates to that of the optimal scheme for the memories with different fault distributions. Also, the ratio of the analysis time to the test time is small.

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主出版物標題Proceedings - Design, Automation and Test in Europe, DATE'06
出版狀態已出版 - 2006
事件Design, Automation and Test in Europe, DATE'06 - Munich, Germany
持續時間: 6 3月 200610 3月 2006

出版系列

名字Proceedings -Design, Automation and Test in Europe, DATE
1
ISSN(列印)1530-1591

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???event.eventtypes.event.conference???Design, Automation and Test in Europe, DATE'06
國家/地區Germany
城市Munich
期間6/03/0610/03/06

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