A 90 nm CMOS low phase noise sub-harmonically injection-locked voltage-controlled oscillator with FLL self-alignment technique

An innovative low phase noise sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with frequency-locked loop (FLL) self-alignment technique is presented in this paper using 90 nm CMOS process. To overcome the issue of narrow locking range, the control voltage of the SILVCO is adaptively adjusted using the FLL technique to refer to the sub-harmonic input frequency. This work demonstrates excellent robustness over temperature variation from 10°C to 70° C. Under the locking condition of the SILVCO with FLL, the measured minimum phase noise is -130.4 dBc/Hz at 1 MHz offset, the measured minimum jitter integrated from 50 kHz to 80 MHz is lower than 30.5 fs, and the output frequency is from 9.9 to 10.4 GHz. The circuit performance can be compared to the advanced CMOS low phase noise clock generators.