A 75-Gb/s/mm² and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm

Keyphrases

• Energy Efficient 100%
• Decoder 100%
• Reduced Complexity 100%
• Low-density Parity-check Codes 100%
• Min-max Algorithm 100%
• Proposed Design 66%
• Power Consumption 66%
• Route Network 66%
• Baseband System 66%
• Bit Error Rate 33%
• High-throughput 33%
• Millimeter Wave 33%
• Design Basis 33%
• CMOS Process 33%
• Area-efficient 33%
• Power Efficiency 33%
• Signal-to-noise Ratio 33%
• Message Passing 33%
• Error Signal 33%
• Wiring 33%
• Switching Activity 33%
• Routing Congestion 33%
• Rate Requirement 33%
• Degree of Parallelism 33%
• Lower Error Rates 33%
• Address Generator 33%
• Min-Sum 33%
• Decoder Design 33%
• Memory Element 33%
• Hardware Optimization 33%
• Normalized Min-sum Algorithm 33%

Engineering

• Bit Error Rate 100%
• Energy Engineering 100%
• Electric Power Utilization 100%
• Network Routing 100%
• Signal-to-Noise Ratio 50%
• Millimeter Wave 50%
• Internals 50%
• Parallelism 50%
• Error Signal 50%
• Switching Activity 50%
• Critical Path 50%
• Address Generator 50%

Computer Science

• Approximation (Algorithm) 100%
• Energy Efficient 100%
• min-sum algorithm 100%
• Power Consumption 50%
• Network Routing 50%
• High Throughput 25%
• Power Efficiency 25%
• Message Passing 25%
• Parallelism 25%
• Critical Path 25%
• Noise-to-Signal Ratio 25%
• Switching Activity 25%
• Routing Congestion 25%
• Internal Message 25%
• Hardware Optimization 25%