A 64-MHz∼640-MHz 64-phase clock generator

Hong Yi Huang, Jen Chieh Liu, Shi Jia Sun, Cheng Hao Fu, Kuo Hsing Cheng

研究成果: 書貢獻/報告類型會議論文篇章同行評審

摘要

This paper proposes a wide-range all-digital phase locked loop (ADPLL) utilizing a successive approximation register-controlled (SAR) architecture. A modified digital to voltage converter (DAC) is adopted to provide a wide supply voltage range for the voltage controlled oscillator (VCO) so that the power consumption of can be reduced and a wide frequency range can be operated. A differential VCO is invented for reducing the jitter. A test chip is implemented using a 0.18μm CMOS process with an area of 500×620um2. The measured frequency range is from 64MHz to 640MHz. The p2p jitter is 20.5 ps and the rms jitter is 2.4 ps.

原文???core.languages.en_GB???
主出版物標題Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014
編輯Serge Bernard, Witold Pleskacz, Dominik Kasprowicz, Lukas Sekanina, Michel Renovell
發行者Institute of Electrical and Electronics Engineers Inc.
頁面51-54
頁數4
ISBN(電子)9781479945580
DOIs
出版狀態已出版 - 30 7月 2014
事件17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014 - Warsaw, Poland
持續時間: 23 4月 201425 4月 2014

出版系列

名字Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014

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???event.eventtypes.event.conference???17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014
國家/地區Poland
城市Warsaw
期間23/04/1425/04/14

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