A 64-MHz∼640-MHz 64-phase clock generator

Hong Yi Huang; Jen Chieh Liu; Shi Jia Sun; Cheng Hao Fu; Kuo Hsing Cheng

doi:10.1109/DDECS.2014.6868762

A 64-MHz∼640-MHz 64-phase clock generator

Hong Yi Huang, Jen Chieh Liu, Shi Jia Sun, Cheng Hao Fu, Kuo Hsing Cheng

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

摘要

This paper proposes a wide-range all-digital phase locked loop (ADPLL) utilizing a successive approximation register-controlled (SAR) architecture. A modified digital to voltage converter (DAC) is adopted to provide a wide supply voltage range for the voltage controlled oscillator (VCO) so that the power consumption of can be reduced and a wide frequency range can be operated. A differential VCO is invented for reducing the jitter. A test chip is implemented using a 0.18μm CMOS process with an area of 500×620um². The measured frequency range is from 64MHz to 640MHz. The p2p jitter is 20.5 ps and the rms jitter is 2.4 ps.

原文	???core.languages.en_GB???
主出版物標題	Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014
編輯	Witold Pleskacz, Michel Renovell, Dominik Kasprowicz, Lukas Sekanina, Serge Bernard
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	51-54
頁數	4
ISBN（電子）	9781479945580
DOIs	https://doi.org/10.1109/DDECS.2014.6868762
出版狀態	已出版 - 30 7月 2014
事件	17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014 - Warsaw, Poland 持續時間: 23 4月 2014 → 25 4月 2014

出版系列

名字	Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014
國家/地區	Poland
城市	Warsaw
期間	23/04/14 → 25/04/14

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10.1109/DDECS.2014.6868762

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Huang, H. Y., Liu, J. C., Sun, S. J., Fu, C. H., & Cheng, K. H. (2014). A 64-MHz∼640-MHz 64-phase clock generator. 於 W. Pleskacz, M. Renovell, D. Kasprowicz, L. Sekanina, & S. Bernard (編輯), Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014 (頁 51-54). 文章 6868762 (Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DDECS.2014.6868762

Huang, Hong Yi ; Liu, Jen Chieh ; Sun, Shi Jia 等. / A 64-MHz∼640-MHz 64-phase clock generator. Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014. 編輯 / Witold Pleskacz ; Michel Renovell ; Dominik Kasprowicz ; Lukas Sekanina ; Serge Bernard. Institute of Electrical and Electronics Engineers Inc., 2014. 頁 51-54 (Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014).

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title = "A 64-MHz∼640-MHz 64-phase clock generator",

abstract = "This paper proposes a wide-range all-digital phase locked loop (ADPLL) utilizing a successive approximation register-controlled (SAR) architecture. A modified digital to voltage converter (DAC) is adopted to provide a wide supply voltage range for the voltage controlled oscillator (VCO) so that the power consumption of can be reduced and a wide frequency range can be operated. A differential VCO is invented for reducing the jitter. A test chip is implemented using a 0.18μm CMOS process with an area of 500×620um2. The measured frequency range is from 64MHz to 640MHz. The p2p jitter is 20.5 ps and the rms jitter is 2.4 ps.",

author = "Huang, {Hong Yi} and Liu, {Jen Chieh} and Sun, {Shi Jia} and Fu, {Cheng Hao} and Cheng, {Kuo Hsing}",

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Huang, HY, Liu, JC, Sun, SJ, Fu, CH & Cheng, KH 2014, A 64-MHz∼640-MHz 64-phase clock generator. 於 W Pleskacz, M Renovell, D Kasprowicz, L Sekanina & S Bernard (編輯), Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014., 6868762, Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014, Institute of Electrical and Electronics Engineers Inc., 頁 51-54, 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014, Warsaw, Poland, 23/04/14. https://doi.org/10.1109/DDECS.2014.6868762

A 64-MHz∼640-MHz 64-phase clock generator. / Huang, Hong Yi; Liu, Jen Chieh; Sun, Shi Jia 等.
Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014. 編輯 / Witold Pleskacz; Michel Renovell; Dominik Kasprowicz; Lukas Sekanina; Serge Bernard. Institute of Electrical and Electronics Engineers Inc., 2014. p. 51-54 6868762 (Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

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AU - Cheng, Kuo Hsing

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N2 - This paper proposes a wide-range all-digital phase locked loop (ADPLL) utilizing a successive approximation register-controlled (SAR) architecture. A modified digital to voltage converter (DAC) is adopted to provide a wide supply voltage range for the voltage controlled oscillator (VCO) so that the power consumption of can be reduced and a wide frequency range can be operated. A differential VCO is invented for reducing the jitter. A test chip is implemented using a 0.18μm CMOS process with an area of 500×620um2. The measured frequency range is from 64MHz to 640MHz. The p2p jitter is 20.5 ps and the rms jitter is 2.4 ps.

AB - This paper proposes a wide-range all-digital phase locked loop (ADPLL) utilizing a successive approximation register-controlled (SAR) architecture. A modified digital to voltage converter (DAC) is adopted to provide a wide supply voltage range for the voltage controlled oscillator (VCO) so that the power consumption of can be reduced and a wide frequency range can be operated. A differential VCO is invented for reducing the jitter. A test chip is implemented using a 0.18μm CMOS process with an area of 500×620um2. The measured frequency range is from 64MHz to 640MHz. The p2p jitter is 20.5 ps and the rms jitter is 2.4 ps.

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Huang HY, Liu JC, Sun SJ, Fu CH, Cheng KH. A 64-MHz∼640-MHz 64-phase clock generator. 於 Pleskacz W, Renovell M, Kasprowicz D, Sekanina L, Bernard S, 編輯, Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 51-54. 6868762. (Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014). doi: 10.1109/DDECS.2014.6868762

A 64-MHz∼640-MHz 64-phase clock generator

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