A 6.4 Gbit/s embedded compression codec for memory-efficient applications on advanced-HD specification

Tsung Han Tsai, Yu Hsuan Lee

研究成果: 雜誌貢獻期刊論文同行評審

22 引文 斯高帕斯(Scopus)

摘要

The embedded compression (EC) technique is applied to reduce the memory bandwidth and capacity in a display system. In this paper, the high-speed EC algorithm is proposed for advanced-HD specification. It mainly comprises three features: 1) the associated geometric-based probability model is developed to construct context-modeling mechanism without context-table; 2) develop content-adaptive Golomb-Rice code and geometric-based binary code as the entropy coding with minor order of context; and 3) provide the rate control mechanism to guarantee the saving ratio of memory bandwidth and capacity. With competitive coding efficiency, the computation-efficiency of the proposed EC algorithm is about 44% and 40% of FELICS and JPEG-LS. The proposed very-large-scale integration architecture of entire codec is implemented in TSMC 0.18- μ m 1P6M CMOS technology. Based on pixel-based parallelism and segment-based parallelism techniques, the encoding/decoding capability reaches Quad Full-high definition (QFHD) (3840×2160) at 30 Hz. The maximum throughput is as high as 6.4 Gbit/s. Furthermore, with multi-level parallelism, the performance can be extended to QHD (2560×1440) at 120 Hz and QFHD at 120 Hz for the double frame rate technique.

原文???core.languages.en_GB???
文章編號5510118
頁(從 - 到)1277-1291
頁數15
期刊IEEE Transactions on Circuits and Systems for Video Technology
20
發行號10
DOIs
出版狀態已出版 - 10月 2010

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