A 6-GHz built-in jitter measurement circuit using multiphase sampler

Kuo Hsing Cheng, Jen Chieh Liu, Hong Yi Huang, Yu Liang Li, Yong Jhen Jhu

研究成果: 雜誌貢獻期刊論文同行評審

9 引文 斯高帕斯(Scopus)

摘要

This brief presents a 6-GHz built-in jitter measurement (BIJM) with the time amplifier (TA) and the multiphase sampler (MPS) to achieve a 1-ps timing resolution. The proposed MPS can reduce the area, and the TA can extend the total timing resolution of BIJM. The self-referenced circuit with the autocalibration technique can eliminate the process variations and create a reference clock being a sampled signal. Using the calibration technique, the gain variation of TA and the timing resolution variation of MPS can be aligned to achieve a 1-ps timing resolution. The sense amplifier delay flip-flop uses the bulk input to reduce the measured error. The BIJM is fabricated by a 90-nm CMOS process. The core area of BIJM is 130 μm × 200 μm, and the power consumption is 20.4 mW with the I/O buffers.

原文???core.languages.en_GB???
文章編號5971770
頁(從 - 到)492-496
頁數5
期刊IEEE Transactions on Circuits and Systems II: Express Briefs
58
發行號8
DOIs
出版狀態已出版 - 8月 2011

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