This study presents a 6-Gb/s clock and data recovery (CDR) for the high-speed data transmission systems. Similar to the concept of the oversampling CDR, the proposed CDR presents an alternative scheme, which uses the data delay window (DDW) and a sensing-amplified phase detector (SAPD) to substitute the conventional DFF-based PD. It shows that the NRZ data could be aligned and recovered by the only one clock instead of the multi-phase clock, and the complexity of the clock distribution network could be mitigated than counterpart. The study has been implemented in TSMC 0.13 um. Operating at the 6-Gb/s data rate and 3-GHz clock frequency, the estimated peak to peak jitter of the recovered clock is 7.55 ps, and the recovered data jitter is less than 6.4 ps. The core area of data recovery (DR) loop occupies 0.291 mm 2. The core power consumption of the all loops including I/O buffer is around 50 mW at the supply voltage of 1.2V.
|出版狀態||已出版 - 2012|
|事件||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of|
持續時間: 20 5月 2012 → 23 5月 2012
|???event.eventtypes.event.conference???||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012|
|國家/地區||Korea, Republic of|
|期間||20/05/12 → 23/05/12|