A 538Mbps 2×64 spatial permutation modulation detector for MIMO systems

Keyphrases

• Multiple-input multiple-output System 100%
• Spatial Permutation Modulation 100%
• Modulation Systems 40%
• Maximum Ratio Combining 40%
• Spatial Modulation 40%
• Multiple Candidates 40%
• Antenna 20%
• Mobile Communication 20%
• Maximum Throughput 20%
• Multiple-input multiple-output 20%
• FPGA chip 20%
• Hardware Implementation 20%
• Implementation Results 20%
• FPGA Implementation 20%
• Transmit Diversity 20%
• Xilinx Virtex 20%
• Throughput Computing 20%
• Artix-7 FPGA 20%
• System Gain 20%
• Next Generation Communication Systems 20%
• Normalized Throughput 20%
• Time Diversity 20%
• Scalable Computing 20%

Computer Science

• multiple-input-multiple-output 100%
• maximal ratio combining 100%
• Field Programmable Gate Arrays 100%
• Hardware Implementation 50%
• Normalized Throughput 50%