A 5-11 GHz CMOS power amplifier using Guanella-type transmission line transformer and adaptive bias circuit

This paper presents a 5-11 GHz fully integrated power amplifier (PA) in tsmc 0.18 μm CMOS technology. The PA utilized broadband and low-loss Guanella differential transmission-line transformers (DTLTs) as the input- and output-matching networks to achieve broadband performance. The adaptive bias circuit was adopted to improve the linearity and power added efficiency (PAE) at power back-off region. The power gain and stability were enhanced by capacitive unilaterialized technique. The PA achieves an output 1-dB compression point (OP_1dB) of 21.75 dBm with 1-dB bandwidth from 5.5 to 10.5 GHz. The PAEs at peak and P_1dB are 21.3% and 23.9%, respectively. The chip dimensions, including all pads, are 1.79 × 1.04 mm².