A 4x4-block level pipeline and bandwidth optimized motion compensation hardware design for H.264/AVC DECODER

De Yuan Shen, Tsung Han Tsai

研究成果: 書貢獻/報告類型會議論文篇章同行評審

5 引文 斯高帕斯(Scopus)

摘要

A 4x4-block level pipeline motion compensation (MC) architecture for H.264/AVC decoder with high hardware utilization and low bandwidth requirement is presented in this paper. With the proposed Minimum Required Reference Data Loading (MRRD) and Data Reuse from Upper/Left block (DRUL) strategies, the memory bandwidth is reduced by 70% without violating the inherent double-z-scan order of H.264/AVC bitstream. The flexible FIR filters and row/column-based interpolation are adopted to enhance the hardware utilization. Besides, to improve the bus utilization and decoding time, an on-chip memory with transpose data access and memory preloaded techniques are used for reference data reuse. The proposed MC hardware can support 1920x1088 30fps 4x4-block level pipeline in H.264/AVC decoder with less than 60MB/s memory bandwidth and a 432-byte on-chip memory when operating at 100MHz.

原文???core.languages.en_GB???
主出版物標題Proceedings - 2009 IEEE International Conference on Multimedia and Expo, ICME 2009
頁面1106-1109
頁數4
DOIs
出版狀態已出版 - 2009
事件2009 IEEE International Conference on Multimedia and Expo, ICME 2009 - New York, NY, United States
持續時間: 28 6月 20093 7月 2009

出版系列

名字Proceedings - 2009 IEEE International Conference on Multimedia and Expo, ICME 2009

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???event.eventtypes.event.conference???2009 IEEE International Conference on Multimedia and Expo, ICME 2009
國家/地區United States
城市New York, NY
期間28/06/093/07/09

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