A 4x4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps

Pei Yun Tsai; Wei Tzuo Chen; Xing Cheng Lin; Meng Yuan Huang

doi:10.1109/ISCAS.2010.5537675

A 4x4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps

Pei Yun Tsai, Wei Tzuo Chen, Xing Cheng Lin, Meng Yuan Huang

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

31 引文斯高帕斯（Scopus）

摘要

In this paper, a VLSI architecture of a reduced-complexity K-best sphere decoder is designed, which aims to solve the 4 x 4 64-QAM multiple-input multiple-output (MIMO) signal detection problems in high-speed applications. We propose a fully-pipelined sorter, which can generate one result per clock cycle and thus greatly enhance the detection throughput. On the other hand, various K values are adopted at each layer to save the hardware complexity. The proposed design has been implemented in 0.18 μm CMOS technology and has 366K gates. From post-layout simulation, this work achieves a detection rate of 1.5 Gbps at 62.5-MHz clock frequency.

原文	???core.languages.en_GB???
主出版物標題	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
主出版物子標題	Nano-Bio Circuit Fabrics and Systems
頁面	3953-3956
頁數	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537675
出版狀態	已出版 - 2010
事件	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France 持續時間: 30 5月 2010 → 2 6月 2010

出版系列

名字	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
國家/地區	France
城市	Paris
期間	30/05/10 → 2/06/10

存取文件

10.1109/ISCAS.2010.5537675

引用此

Tsai, P. Y., Chen, W. T., Lin, X. C., & Huang, M. Y. (2010). A 4x4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps. 於 ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (頁 3953-3956). 文章 5537675 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537675

@inproceedings{2b517b3954664d8ea7e39180228d329a,

title = "A 4x4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps",

abstract = "In this paper, a VLSI architecture of a reduced-complexity K-best sphere decoder is designed, which aims to solve the 4 x 4 64-QAM multiple-input multiple-output (MIMO) signal detection problems in high-speed applications. We propose a fully-pipelined sorter, which can generate one result per clock cycle and thus greatly enhance the detection throughput. On the other hand, various K values are adopted at each layer to save the hardware complexity. The proposed design has been implemented in 0.18 μm CMOS technology and has 366K gates. From post-layout simulation, this work achieves a detection rate of 1.5 Gbps at 62.5-MHz clock frequency.",

author = "Tsai, {Pei Yun} and Chen, {Wei Tzuo} and Lin, {Xing Cheng} and Huang, {Meng Yuan}",

year = "2010",

doi = "10.1109/ISCAS.2010.5537675",

language = "???core.languages.en_GB???",

isbn = "9781424453085",

series = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems",

pages = "3953--3956",

booktitle = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems",

note = "2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 ; Conference date: 30-05-2010 Through 02-06-2010",

}

Tsai, PY, Chen, WT, Lin, XC & Huang, MY 2010, A 4x4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps. 於 ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537675, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, 頁 3953-3956, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 30/05/10. https://doi.org/10.1109/ISCAS.2010.5537675

A 4x4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps. / Tsai, Pei Yun; Chen, Wei Tzuo; Lin, Xing Cheng 等.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3953-3956 5537675 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

TY - GEN

T1 - A 4x4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps

AU - Tsai, Pei Yun

AU - Chen, Wei Tzuo

AU - Lin, Xing Cheng

AU - Huang, Meng Yuan

PY - 2010

Y1 - 2010

N2 - In this paper, a VLSI architecture of a reduced-complexity K-best sphere decoder is designed, which aims to solve the 4 x 4 64-QAM multiple-input multiple-output (MIMO) signal detection problems in high-speed applications. We propose a fully-pipelined sorter, which can generate one result per clock cycle and thus greatly enhance the detection throughput. On the other hand, various K values are adopted at each layer to save the hardware complexity. The proposed design has been implemented in 0.18 μm CMOS technology and has 366K gates. From post-layout simulation, this work achieves a detection rate of 1.5 Gbps at 62.5-MHz clock frequency.

AB - In this paper, a VLSI architecture of a reduced-complexity K-best sphere decoder is designed, which aims to solve the 4 x 4 64-QAM multiple-input multiple-output (MIMO) signal detection problems in high-speed applications. We propose a fully-pipelined sorter, which can generate one result per clock cycle and thus greatly enhance the detection throughput. On the other hand, various K values are adopted at each layer to save the hardware complexity. The proposed design has been implemented in 0.18 μm CMOS technology and has 366K gates. From post-layout simulation, this work achieves a detection rate of 1.5 Gbps at 62.5-MHz clock frequency.

UR - http://www.scopus.com/inward/record.url?scp=77955997174&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2010.5537675

DO - 10.1109/ISCAS.2010.5537675

M3 - 會議論文篇章

AN - SCOPUS:77955997174

SN - 9781424453085

T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

SP - 3953

EP - 3956

BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems

T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010

Y2 - 30 May 2010 through 2 June 2010

ER -

Tsai PY, Chen WT, Lin XC, Huang MY. A 4x4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps. 於 ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3953-3956. 5537675. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). doi: 10.1109/ISCAS.2010.5537675

A 4x4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps

摘要

出版系列

???event.eventtypes.event.conference???

存取文件

指紋

引用此