A 4x4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps

Pei Yun Tsai, Wei Tzuo Chen, Xing Cheng Lin, Meng Yuan Huang

研究成果: 書貢獻/報告類型會議論文篇章同行評審

29 引文 斯高帕斯(Scopus)

摘要

In this paper, a VLSI architecture of a reduced-complexity K-best sphere decoder is designed, which aims to solve the 4 x 4 64-QAM multiple-input multiple-output (MIMO) signal detection problems in high-speed applications. We propose a fully-pipelined sorter, which can generate one result per clock cycle and thus greatly enhance the detection throughput. On the other hand, various K values are adopted at each layer to save the hardware complexity. The proposed design has been implemented in 0.18 μm CMOS technology and has 366K gates. From post-layout simulation, this work achieves a detection rate of 1.5 Gbps at 62.5-MHz clock frequency.

原文???core.languages.en_GB???
主出版物標題ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
主出版物子標題Nano-Bio Circuit Fabrics and Systems
頁面3953-3956
頁數4
DOIs
出版狀態已出版 - 2010
事件2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
持續時間: 30 5月 20102 6月 2010

出版系列

名字ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

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???event.eventtypes.event.conference???2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
國家/地區France
城市Paris
期間30/05/102/06/10

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