A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Shyh Shyuan Sheu, Meng Fan Chang, Ku Feng Lin, Che Wei Wu, Yu Sheng Chen, Pi Feng Chiu, Chia Chen Kuo, Yih Shan Yang, Pei Chia Chiang, Wen Pin Lin, Che He Lin, Heng Yuan Lee, Pei Yi Gu, Sum Min Wang, Frederick T. Chen, Keng Li Su, Chen Hsin Lien, Kuo Hsing Cheng, Hsin Tun Wu, Tzu Kun KuMing Jer Kao, Ming Jinn Tsai

研究成果: 書貢獻/報告類型會議論文篇章同行評審

228 引文 斯高帕斯(Scopus)

摘要

Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1-3], MRAM [4-5], and resistive RAM (RRAM) [6-8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

原文???core.languages.en_GB???
主出版物標題2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
發行者Institute of Electrical and Electronics Engineers Inc.
頁面200-202
頁數3
ISBN(列印)9781612843001
DOIs
出版狀態已出版 - 2011
事件2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, United States
持續時間: 20 2月 201124 2月 2011

出版系列

名字Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN(列印)0193-6530

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???event.eventtypes.event.conference???2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
國家/地區United States
城市San Francisco
期間20/02/1124/02/11

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