A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Shyh Shyuan Sheu; Meng Fan Chang; Ku Feng Lin; Che Wei Wu; Yu Sheng Chen; Pi Feng Chiu; Chia Chen Kuo; Yih Shan Yang; Pei Chia Chiang; Wen Pin Lin; Che He Lin; Heng Yuan Lee; Pei Yi Gu; Sum Min Wang; Frederick T. Chen; Keng Li Su; Chen Hsin Lien; Kuo Hsing Cheng; Hsin Tun Wu; Tzu Kun Ku; Ming Jer Kao; Ming Jinn Tsai

doi:10.1109/ISSCC.2011.5746281

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Shyh Shyuan Sheu, Meng Fan Chang, Ku Feng Lin, Che Wei Wu, Yu Sheng Chen, Pi Feng Chiu, Chia Chen Kuo, Yih Shan Yang, Pei Chia Chiang, Wen Pin Lin, Che He Lin, Heng Yuan Lee, Pei Yi Gu, Sum Min Wang, Frederick T. Chen, Keng Li Su, Chen Hsin Lien, Kuo Hsing Cheng, Hsin Tun Wu, Tzu Kun KuMing Jer Kao, Ming Jinn Tsai

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

233 引文斯高帕斯（Scopus）

摘要

Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1-3], MRAM [4-5], and resistive RAM (RRAM) [6-8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (V_BL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

原文	???core.languages.en_GB???
主出版物標題	2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	200-202
頁數	3
ISBN（列印）	9781612843001
DOIs	https://doi.org/10.1109/ISSCC.2011.5746281
出版狀態	已出版 - 2011
事件	2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, United States 持續時間: 20 2月 2011 → 24 2月 2011

出版系列

名字	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN（列印）	0193-6530

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
國家/地區	United States
城市	San Francisco
期間	20/02/11 → 24/02/11

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10.1109/ISSCC.2011.5746281

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Sheu, S. S., Chang, M. F., Lin, K. F., Wu, C. W., Chen, Y. S., Chiu, P. F., Kuo, C. C., Yang, Y. S., Chiang, P. C., Lin, W. P., Lin, C. H., Lee, H. Y., Gu, P. Y., Wang, S. M., Chen, F. T., Su, K. L., Lien, C. H., Cheng, K. H., Wu, H. T., ... Tsai, M. J. (2011). A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. 於 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011 (頁 200-202). 文章 5746281 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2011.5746281

Sheu, Shyh Shyuan ; Chang, Meng Fan ; Lin, Ku Feng 等. / A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. Institute of Electrical and Electronics Engineers Inc., 2011. 頁 200-202 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

@inproceedings{5c5aacc8375e495a96c00eb8a771427e,

title = "A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability",

abstract = "Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1-3], MRAM [4-5], and resistive RAM (RRAM) [6-8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.",

author = "Sheu, {Shyh Shyuan} and Chang, {Meng Fan} and Lin, {Ku Feng} and Wu, {Che Wei} and Chen, {Yu Sheng} and Chiu, {Pi Feng} and Kuo, {Chia Chen} and Yang, {Yih Shan} and Chiang, {Pei Chia} and Lin, {Wen Pin} and Lin, {Che He} and Lee, {Heng Yuan} and Gu, {Pei Yi} and Wang, {Sum Min} and Chen, {Frederick T.} and Su, {Keng Li} and Lien, {Chen Hsin} and Cheng, {Kuo Hsing} and Wu, {Hsin Tun} and Ku, {Tzu Kun} and Kao, {Ming Jer} and Tsai, {Ming Jinn}",

year = "2011",

doi = "10.1109/ISSCC.2011.5746281",

language = "???core.languages.en_GB???",

isbn = "9781612843001",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "200--202",

booktitle = "2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011",

note = "2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 ; Conference date: 20-02-2011 Through 24-02-2011",

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Sheu, SS, Chang, MF, Lin, KF, Wu, CW, Chen, YS, Chiu, PF, Kuo, CC, Yang, YS, Chiang, PC, Lin, WP, Lin, CH, Lee, HY, Gu, PY, Wang, SM, Chen, FT, Su, KL, Lien, CH, Cheng, KH, Wu, HT, Ku, TK, Kao, MJ & Tsai, MJ 2011, A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. 於 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011., 5746281, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., 頁 200-202, 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, San Francisco, United States, 20/02/11. https://doi.org/10.1109/ISSCC.2011.5746281

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. / Sheu, Shyh Shyuan; Chang, Meng Fan; Lin, Ku Feng 等.
2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. Institute of Electrical and Electronics Engineers Inc., 2011. p. 200-202 5746281 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

TY - GEN

T1 - A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

AU - Sheu, Shyh Shyuan

AU - Chang, Meng Fan

AU - Lin, Ku Feng

AU - Wu, Che Wei

AU - Chen, Yu Sheng

AU - Chiu, Pi Feng

AU - Kuo, Chia Chen

AU - Yang, Yih Shan

AU - Chiang, Pei Chia

AU - Lin, Wen Pin

AU - Lin, Che He

AU - Lee, Heng Yuan

AU - Gu, Pei Yi

AU - Wang, Sum Min

AU - Chen, Frederick T.

AU - Su, Keng Li

AU - Lien, Chen Hsin

AU - Cheng, Kuo Hsing

AU - Wu, Hsin Tun

AU - Ku, Tzu Kun

AU - Kao, Ming Jer

AU - Tsai, Ming Jinn

PY - 2011

Y1 - 2011

N2 - Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1-3], MRAM [4-5], and resistive RAM (RRAM) [6-8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

AB - Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1-3], MRAM [4-5], and resistive RAM (RRAM) [6-8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

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U2 - 10.1109/ISSCC.2011.5746281

DO - 10.1109/ISSCC.2011.5746281

M3 - 會議論文篇章

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SN - 9781612843001

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

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BT - 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011

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ER -

Sheu SS, Chang MF, Lin KF, Wu CW, Chen YS, Chiu PF 等. A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. 於 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. Institute of Electrical and Electronics Engineers Inc. 2011. p. 200-202. 5746281. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2011.5746281

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

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