We present a new Vth-mismatched loadless 4T SRAM TRNG MACRO. The MACRO includes 2 sub-arrays. 1 array comprises 16× 16 4T-SRAM cells. Instead of latch-effect, process-induced Vth- mismatch is as entropy of the TRNG in 40-nm CMOS technology. Since 4T-SRAM is volatile, 'read-just-after-write' (RAW) scheme is designed to readout random bits immediately after bits are just written, and the DQ-FF parallel-in-and-series-out (PISO) is to register random-bits to output. We execute the RAW scheme in 16 cells in the same row for both arrays simultaneously to generate 32 random bits at once, in terms of 32x bandwidth expansion. Results show that good-quality random-bits can be generated at rmVBL=0.65rmV;\ rmVWL=0.85rmV in 6ns with 400 MHz of clock, in terms of 0% of bit-error-rate; 49.91% of mean with 4.63% of standard deviation for the Hamming-distance; 50% of the Hamming-weight; 0.9997 of entropy. Moreover, energy efficiency is 0.82 pJ/b n; performance is 3.64 TOP/W.