A 30PHASE 500MHZ PLL for 3X over-sampling clock data recovery

Kuo Hsing Cheng, Chao An Chen, Wei Bin Yang, Feng Hsin Cho

研究成果: 書貢獻/報告類型會議論文篇章同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this paper, we present architecture of phase-locked loop (PLL) for clock and data recovery (CDR) for high-speed serial links. The conventional over-sampling architecture uses two timing modules. One is used to track reference clock, the other is to generate multiphase to sample high speed serial-in data. The architecture improves drawback of the conventional CDR by using Blender unit to make high resolution delay phase and PLL will track this phase. Additionally, this work achieves to save power and chip area and the stability of system can be improved, because of combining the two timing modules to one. This work is fabricated by TSMC 0.13um 1p.8m 1.2v process. The PLL is operates at 500MHz and CDR circuit can recovery 5Gb/s serial-in data.

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主出版物標題2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs
出版狀態已出版 - 2007
事件2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan
持續時間: 25 4月 200727 4月 2007

出版系列

名字2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

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???event.eventtypes.event.conference???2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
國家/地區Taiwan
城市Hsinchu
期間25/04/0727/04/07

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