A 30-GHz 10-dB low noise amplifier using standard 0.18-μm CMOS technology

Hsin Lung Tu; Tsung Yu Yang; Kung Hao Liang; Hwann Kaeo Chiou

doi:10.1002/mop.22226

A 30-GHz 10-dB low noise amplifier using standard 0.18-μm CMOS technology

Hsin Lung Tu, Tsung Yu Yang, Kung Hao Liang, Hwann Kaeo Chiou

電機工程學系

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

A three-stage 30-GHz law noise amplifier (LNA) was designed and fabricated in a standard 0.18-μm CMOS technology. The LNA has demonstrated a 10-dB gain and a minimum noise figure of 5.2 dB at 30 GHz. The achieved input 1-dB compression point (IP_{1 dB}) and third order intercept point (IP3) are -7 and +2.5 dBm, with total current of 16 mA from a 1.5-V power supply. To the author's knowledge, the LNA shows the best overall performances ever reported in standard0.18-μm CMOS process.

原文	???core.languages.en_GB???
頁（從 - 到）	647-649
頁數	3
期刊	Microwave and Optical Technology Letters
卷	49
發行號	3
DOIs	https://doi.org/10.1002/mop.22226
出版狀態	已出版 - 3月 2007

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10.1002/mop.22226

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abstract = "A three-stage 30-GHz law noise amplifier (LNA) was designed and fabricated in a standard 0.18-μm CMOS technology. The LNA has demonstrated a 10-dB gain and a minimum noise figure of 5.2 dB at 30 GHz. The achieved input 1-dB compression point (IP1 dB) and third order intercept point (IP3) are -7 and +2.5 dBm, with total current of 16 mA from a 1.5-V power supply. To the author's knowledge, the LNA shows the best overall performances ever reported in standard0.18-μm CMOS process.",

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AB - A three-stage 30-GHz law noise amplifier (LNA) was designed and fabricated in a standard 0.18-μm CMOS technology. The LNA has demonstrated a 10-dB gain and a minimum noise figure of 5.2 dB at 30 GHz. The achieved input 1-dB compression point (IP1 dB) and third order intercept point (IP3) are -7 and +2.5 dBm, with total current of 16 mA from a 1.5-V power supply. To the author's knowledge, the LNA shows the best overall performances ever reported in standard0.18-μm CMOS process.

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A 30-GHz 10-dB low noise amplifier using standard 0.18-μm CMOS technology

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