A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit

Kuo Hsing Cheng, Shu Ming Chang, Shu Yu Jiang, Wei Bin Yang

研究成果: 雜誌貢獻會議論文同行評審

10 引文 斯高帕斯(Scopus)

摘要

This paper describes a fully differential DLL-based frequency multiplier using a noise-rejected voltage-controlled delay line (VCDL). In order to improve the power consumption and synthesized frequency range of the DLLbased frequency multiplier, we design an edge combiner using current mode logic to generate fully differential output clock. This edge combiner consists of four stage fully differential current logic with XOR scheme. It can obtain the characteristic of high speed operation. Based on TSMC 0.18um 1P6M N-well CMOS process, the simulation results show that the DLL can operate from 360 to 550MH z. And,the frequency multiplier can synthesize frequency from 720MH z to 2.2GH z. Proposed frequency multiplier produces the 2x and 4x fully differential output clock frequency. The total power dissipation is only 38mW and the cycle-to-cycle jitter is less than 17ps.

原文???core.languages.en_GB???
文章編號1464803
頁(從 - 到)1174-1177
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態已出版 - 2005
事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
持續時間: 23 5月 200526 5月 2005

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