A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization

Ting Chen Wei, Wei Chang Liu, Chi Yao Tseng, Syu Siang Long, Shyh Jye Jou, Muh Tian Shiue

研究成果: 雜誌貢獻會議論文同行評審

3 引文 斯高帕斯(Scopus)

摘要

An OFDM baseband receiver chip for DVB-T/H application is proposed In this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200ppm sampling clock offset (SCO) and ± 50 subcarrier spacing carrier frequency offset (CFO) In multipath environment. The total memory requirement of this chip is 102.8KB and the total equivalent gate count (Including memory) is about 806,800 gates. By using 0.18μm CMOS process, the power consumption is 28mW at 1.45 V, 40MHz and core size of this chip is 3600μm × 3600μm.

原文???core.languages.en_GB???
文章編號4672094
頁(從 - 到)351-354
頁數4
期刊Proceedings of the Custom Integrated Circuits Conference
DOIs
出版狀態已出版 - 2008
事件IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States
持續時間: 21 9月 200824 9月 2008

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