A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN

Keyphrases

• IEEE 802.16 100%
• FFT-IFFT 100%
• Dataflow Scheduling 100%
• CMOS Technology 33%
• Hardware Efficiency 33%
• Hardware Complexity 33%
• Maximum Throughput 33%
• Noise Ratio 33%
• Pipeline Stages 33%
• Operating Frequency 33%
• 64QAM 33%
• Post-layout Simulation 33%
• Scheduling Techniques 33%
• FPGA Board 33%
• QAM Signals 33%
• Mixed-radix 33%
• Butterfly Unit 33%
• Quantization Noise 33%

Engineering

• Multiple-Input Multiple-Output 100%
• Simulation Result 50%
• Operating Frequency 50%
• Field Programmable Gate Arrays 50%
• Hardware Complexity 50%
• Noise Ratio 50%
• Data Sequence 50%
• Quantization Noise 50%
• Quadrature Phase Shift Keying 50%

Computer Science

• IEEE 802.16 100%
• MIMO Systems 100%
• Computer Hardware 66%
• Operating Frequency 33%
• Quantization Noise 33%
• Pipeline Stage 33%
• Field Programmable Gate Arrays 33%
• Quadrature Phase Shift Keying 33%