@inproceedings{a39e02349a264cc89bb904c08dd6b543,
title = "A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN",
abstract = "In this paper, an efficient solution of MIMO FFT/IFFT processor for IEEE 802.16 WMAN is presented. By applying the proposed mixed-radix dataflow scheduling (MRDS) technique, the effective hardware utilization can be raised to 100%. Therefore, a single butterfly unit within each pipeline stage is sufficient to deal with the two data sequences, and the hardware complexity is significantly reduced. The proposed FFT/IFFT processor has been emulated on the FPGA board. The signalto-quantization noise ratio (SQNR) is over 44 dB for QPSK and 16/64-QAM signals. Furthermore, a test chip has been designed using standard 0.18-μm CMOS technology with a core area of 887×842 μm2. According to the post-layout simulation results, the design consumes 46 mW at 64 MHz operating frequency, which meets the maximum throughput requirements of IEEE 802.16 WMAN.",
author = "Yuan, {Fang Li} and Lin, {Yi Hsien} and Wu, {Chih Feng} and Shiue, {Muh Tian} and Wang, {Chorng Kuang}",
year = "2008",
doi = "10.1109/ASSCC.2008.4708789",
language = "???core.languages.en_GB???",
isbn = "9781424426058",
series = "Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008",
pages = "309--312",
booktitle = "Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008",
note = "2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 ; Conference date: 03-11-2008 Through 05-11-2008",
}