A 2.5-GHz Built-in jitter measurement system in a serial-link transceiver

Shu Yu Jiang, Kuo Hsing Cheng, Pei Yi Jian

研究成果: 雜誌貢獻期刊論文同行評審

14 引文 斯高帕斯(Scopus)

摘要

A 2.5-GHz built-in jitter measurement (BIJM) system is adopted to measure the clock jitter on a transmitter and receiver. The proposed Vernier caliper and autofocus approaches reduce the area cost of delay cells by 48.78% relative to pure Vernier delay line structure with a wide measurement range. The counter circuit occupies an area of 19 μm × 61 μ m in the traditional stepping scan approach. The proposed equivalent-signal sampling technique removes the input jitter transfer path from the sampling clock. The power supply rejection design is incorporated into the delay cell and the judge circuit. The layout implementation, calibration, and test time of the proposed BIJM system are all improved. The core circuit occupies an area of only 0.5 mm × 0.15 mm with the 90-nm CMOS process. The Gaussian and uniform distributions jitter is verified at a 5-ps timing resolution and a 2.5-GHz input clock frequency.

原文???core.languages.en_GB???
文章編號5152959
頁(從 - 到)1698-1708
頁數11
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
17
發行號12
DOIs
出版狀態已出版 - 12月 2009

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