A 25-75 GHz miniature double balanced frequency doubler in 0.18-μm CMOS technology

Tsung Yu Yang, Hwann Kaeo Chiou

研究成果: 雜誌貢獻期刊論文同行評審

21 引文 斯高帕斯(Scopus)

摘要

A 25-75 GHz compact double balanced frequency doubler fabricated in standard 0.18-μm CMOS process is demonstrated. The resistive doubler is composed of two identical asymmetric broadside-coupled baluns, and a quad GS-connected diode. The fabricated doubler achieves a radio frequency bandwidth from 25 to 75 GHz with a maximum output power better than +3 dBm; the fundamental signal rejection is ranging from 32 to 59 dB, and only occupies a chip size of 0.24 mm2. To the knowledge of the authors, this double balanced frequency doubler is the first demonstration with an operating frequency up to 75 GHz in 0.18-μm CMOS technology and shows this silicon-based frequency doubler can compare with its GaAs counterpart.

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文章編號4469941
頁(從 - 到)275-277
頁數3
期刊IEEE Microwave and Wireless Components Letters
18
發行號4
DOIs
出版狀態已出版 - 4月 2008

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