A 23-30 GHz Low-Phase-Noise 5-Bit Voltage-Controlled Oscillator in 90-nm CMOS Process

Po Yuan Chen, Jun Liang Chen, Hong Yeh Chang

研究成果: 書貢獻/報告類型會議論文篇章同行評審

摘要

In this paper, a Ka-band 5-bit voltage-controlled oscillator (VCO) is presented using a 90-nm CMOS process. The proposed VCO is composed of 5-bit switched-capacitor array (SCA) and 1-bit switchable varactor array to achieve a wide tuning range of 27.5% and an excellent tuning figure-of-merit (FoMT) of -193.1 dBc/Hz. The proposed 5-bit VCO also demonstrates a lowest phase noise of -103.5 dBc/Hz at 1-MHz offset frequency, corresponding to a FoMPN of -184.4 dBc/Hz. The measured oscillation frequency is from 22.6 to 29.8 GHz with a differential output power of higher than -3 dBm. The chip size is 0.94 0.81 mm2. The core dc power consumption is merely 3 mW with a supply voltage of 0.6 V. The circuit performances can be compared to the reported silicon-based advanced VCOs.

原文???core.languages.en_GB???
主出版物標題2024 IEEE Radio and Wireless Week, RWW 2024 - 2024 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2024
發行者Institute of Electrical and Electronics Engineers Inc.
頁面79-82
頁數4
ISBN(電子)9798350343304
DOIs
出版狀態已出版 - 2024
事件24th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2024 - San Antonio, United States
持續時間: 21 1月 202424 1月 2024

出版系列

名字2024 IEEE Radio and Wireless Week, RWW 2024 - 2024 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2024

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???event.eventtypes.event.conference???24th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2024
國家/地區United States
城市San Antonio
期間21/01/2424/01/24

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