A 2.2-2.4 GHz self-aligned sub-harmonically injection-locked phase-locked loop using 65 nm CMOS process

Yen Liang Yeh, Cheng Han Lu, Meng Han Li, Hong Yeh Chang, Kevin Chen

研究成果: 書貢獻/報告類型會議論文篇章同行評審

1 引文 斯高帕斯(Scopus)

摘要

A 2.2-2.4 GHz self-aligned sub-harmonically injection-locked phase-locked loop (PLL) using 65 nm CMOS process is presented in this paper. A delay-locked loop is employed in the proposed PLL to automatically align the phase difference between the injection signal and the sub-harmonically injection-locked voltage controlled oscillator. At 2.3 GHz, the measured phase noises at 1 kHz, 10 kHz, 100 kHz, and 1 MHz offset are better than-110,-112,-122 and-128.4 dBc/Hz, respectively, with an rms jitter of 228 fs. This work demonstrates low phase noise, low jitter, and good robustness over frequency and temperature variations.

原文???core.languages.en_GB???
主出版物標題European Microwave Week 2014
主出版物子標題"Connecting the Future", EuMW 2014 - Conference Proceedings; EuMIC 2014: 9th European Microwave Integrated Circuits Conference
發行者Institute of Electrical and Electronics Engineers Inc.
頁面269-272
頁數4
ISBN(電子)9782874870361
DOIs
出版狀態已出版 - 23 12月 2014
事件9th European Microwave Integrated Circuits Conference, EuMIC 2014 - Held as Part of the 17th European Microwave Week, EuMW 2014 - Rome, Italy
持續時間: 6 10月 20147 10月 2014

出版系列

名字European Microwave Week 2014: "Connecting the Future", EuMW 2014 - Conference Proceedings; EuMIC 2014: 9th European Microwave Integrated Circuits Conference

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???event.eventtypes.event.conference???9th European Microwave Integrated Circuits Conference, EuMIC 2014 - Held as Part of the 17th European Microwave Week, EuMW 2014
國家/地區Italy
城市Rome
期間6/10/147/10/14

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