A 1.8-V monolithic sige HBT power amplifier with a novel proposed linearizing bias circuit

Ping Chun Yeh, Kuei Cheng Lin, C. Y. Lee, Hwann Kaeo Chiou

研究成果: 會議貢獻類型會議論文同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this work, we report a novel linearization technique by using an on-chip linearizer. The linearizer consists of an SiGe heterojunction bipolar transistors active bias circuit with a MOSFET feedback junction capacitor, which significantly improves the gain compression and phase distortion without additional dc consumption. The proposed circuit topology will find extensive applications in high efficiency and linearity power amplifier design. The power amplifier is implemented by using TSMC 0.18 μm SiGe HBT technology. The compact VBIC model of SiGe HBT was successfully established for the circuit design, and then a 2 GHz power amplifier was designed for demonstrating the circuit performances. The HBT power amplifier exhibits an output power over 20 dBm with a power-added efficiency higher than 42.4% under 1.8 volt operation.

原文???core.languages.en_GB???
頁面305-308
頁數4
出版狀態已出版 - 2004
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
持續時間: 6 12月 20049 12月 2004

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???event.eventtypes.event.conference???2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家/地區Taiwan
城市Tainan
期間6/12/049/12/04

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