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A 1-V 5-GHz self-bias folded-switch mixer in 90-nm CMOS for WLAN receiver
Hwann Kaeo Chiou
, Kuei Cheng Lin, Wei Hsien Chen, Ying Zong Juang
電機工程學系
研究成果
:
雜誌貢獻
›
期刊論文
›
同行評審
35
引文 斯高帕斯(Scopus)
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深入研究「A 1-V 5-GHz self-bias folded-switch mixer in 90-nm CMOS for WLAN receiver」主題。共同形成了獨特的指紋。
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Keyphrases
90-nm CMOS Technology
100%
Bias Current
33%
Conversion Gain
100%
Current Reuse Technique
33%
Differential Low Noise Amplifier
33%
Direct Conversion Receiver
100%
Double-balanced Mixer
66%
IIP2
66%
IIP3
100%
Intercept Point
33%
Low Power Technology
33%
Low Voltage
33%
Mixer
100%
Noise Figure
66%
Polyphase Filter
33%
Port Isolation
66%
Power Consumption
33%
Process Variation
33%
Self-bias
100%
Supply Voltage
33%
Third-order Intermodulation
33%
Transconductance Stage
33%
V(V)
100%
WLAN Receiver
100%
Engineering
Balanced Mixer
66%
Conversion Gain
100%
Direct Conversion Receiver
100%
Electric Power Utilization
33%
Intermodulation
33%
Low Noise Amplifier
33%
Mixers (Machinery)
100%
Noise Figure
66%
Phase Filter
33%
Power Engineering
33%
Process Variation
33%
Supply Voltage
33%
Earth and Planetary Sciences
Intermodulation
25%
Low Noise
25%
Port
100%
Transconductance
25%