A 1-V 5-GHz self-bias folded-switch mixer in 90-nm CMOS for WLAN receiver

Hwann Kaeo Chiou, Kuei Cheng Lin, Wei Hsien Chen, Ying Zong Juang

研究成果: 雜誌貢獻期刊論文同行評審

34 引文 斯高帕斯(Scopus)

摘要

A 5 GHz double balanced mixer (DBM) is implemented in standard 90 nm CMOS low-power technology. A novel low-voltage self-bias current reuse technique is proposed in the RF transconductance stage to obtain better third-order intermodulation intercept point (IIP3 ) and conversion gain (CG) when considering the process variations. The DBM achieves a CG of 12 dB, a noise figure (NF) of 10.6 dB and port-to-port isolations of better than 50 dB. The input second-order (IIP2) and IIP3 are 48 dBm and 4 dBm, respectively. Two I/Q DBMs are then integrated with a differential low-noise amplifier (DLNA) and a poly-phase filter, to from a direct-conversion receiver (DCR). The DCR achieves a CG of 26 dB with an NF of 2.7 dB at 21 mW power consumption from a 1 V supply voltage. The port-to-port isolations are better than 50 dB. The IIP2 and the IIP3 of the DCR are 33 dBm and -12 dBm, respectively.

原文???core.languages.en_GB???
文章編號6104398
頁(從 - 到)1215-1227
頁數13
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
59
發行號6
DOIs
出版狀態已出版 - 2012

指紋

深入研究「A 1-V 5-GHz self-bias folded-switch mixer in 90-nm CMOS for WLAN receiver」主題。共同形成了獨特的指紋。

引用此