摘要
This paper proposes a low supply voltage all-digital clock-deskew buffer with in-phase and quadrature phase (I/Q) outputs on an intra-chip. In some application-specific integrated chips or silicon intellectual properties might enter hibernation mode to conserve energy. The long locking time induces a large standby current, which results in greater power consumption. Furthermore, I/Q clock signals are widely adopted in the communication systems and double data rate memories. The proposed all-digital clock-deskew buffer can operate from 220 to 570 MHz at 0.5 V and the power consumption is 1.95 mW at 570 MHz. This buffer can also supply a quadrature phase output using a proposed two-step edge detector.
原文 | ???core.languages.en_GB??? |
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頁(從 - 到) | 157-167 |
頁數 | 11 |
期刊 | Analog Integrated Circuits and Signal Processing |
卷 | 93 |
發行號 | 1 |
DOIs | |
出版狀態 | 已出版 - 1 10月 2017 |