A 0.3-V all digital crystal-less clock generator for energy harvester applications

Jen Chieh Liu, Wei Chun Lee, Hong Yi Huang, Kuo Hsing Cheng, Chao Jen Huang, Yu Wei Liang, Jia Hung Peng, Yuan Hua Chu

研究成果: 會議貢獻類型會議論文同行評審

8 引文 斯高帕斯(Scopus)

摘要

A 0.3 V all digital crystal-less clock generator (CLCG) is presented for a hearing aid application. The all digital CLCG uses frequency difference between the ring oscillator and the digital controlled oscillator (DCO) to create a mapping table under process and temperature variations. The digital loop filter (DLF) adopts a successive-approximation register (SAR) algorithm for fast locking time. Thus, the worse case of locking time is 73 output cycles. For a hearing aid application, the core area of CLCG and hearing aid system are 62 × 78 μm2 and 1900 × 1920 μm2, respectively, in 65 nm CMOS process. The frequency accuracy is 12 MHz ±3.5% in four test chips. The power consumption is 5 μW. In the period jitter, the RMS and peak-to-peak jitters are 326.4 ps and 2.05 ns, respectively. The frequency drift is smaller than ±4.3% from 0 to 100°C. Thus, this work is also used for energy harvester applications.

原文???core.languages.en_GB???
頁面117-120
頁數4
DOIs
出版狀態已出版 - 2012
事件2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan
持續時間: 12 11月 201214 11月 2012

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
國家/地區Japan
城市Kobe
期間12/11/1214/11/12

指紋

深入研究「A 0.3-V all digital crystal-less clock generator for energy harvester applications」主題。共同形成了獨特的指紋。

引用此