A 0.18-μm dual-gate CMOS device modeling and applications for RF cascode circuits

Hong Yeh Chang, Kung Hao Liang

研究成果: 雜誌貢獻期刊論文同行評審

9 引文 斯高帕斯(Scopus)

摘要

A merged-diffusion dual-gate CMOS device model is presented in this paper. The proposed large-signal model consists of two intrinsic BSIM3v3 nonlinear models and parasitic components. The parasitic elements, including the substrate networks, the distributed resistances, and the inductances, are extracted from the measured S-parameters. In order to verify the model accuracy, a cascode configuration with the proposed dual-gate device is employed in a low-noise amplifier. The dual-gate model is also evaluated with power sweep and loadpull measurements. In addition, a doubly balanced dual-gate mixer is successfully demonstrated using the proposed model. The measured results agree with the simulated results using the proposed device model for both linear and nonlinear applications. The advanced large-signal dual-gate CMOS model can be further used as an RF sub-circuit cell for simplifying the design procedure.

原文???core.languages.en_GB???
文章編號5654608
頁(從 - 到)116-124
頁數9
期刊IEEE Transactions on Microwave Theory and Techniques
59
發行號1
DOIs
出版狀態已出版 - 1月 2011

指紋

深入研究「A 0.18-μm dual-gate CMOS device modeling and applications for RF cascode circuits」主題。共同形成了獨特的指紋。

引用此