A 0.06-ps_RMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation

A 90-nm CMOS, 6-GHz spread-spectrum clock generator (SSCG) showing low jitter and the feasible electromagnetic interference (EMI) reduction is presented. Forsaking the commonly used ΔΣ technique for the average fractional-N ratios by the dithering, the proposed SSCG uses a phase-rotating technique to realize truly fractional division ratios, and creates the spread-spread clocking (SSC) by modulating the fractional-N ratios. The phase-rotating technique effectively calibrates instantaneous timing error and shows ignorable quantization error. Operating at a 6-GHz clock rate, the measured RMS jitter with and without a 0.5% (5000-ppm) down-spreading spectrum are 0.77 ps and 0.71 ps, respectively, showing a significant improvement in the suppressed sub-1ps RMS jitter and the mere increase in RMS jitter of 0.06 ps while implementing SSC. As the serial AT attachment (SATA) standard suggesting the 100 kHz-RBW for the instruments, the measured power attenuation of EMI is 16.12 dB under a 5000-ppm frequency deviation. The chip core area is less than 0.55 × 0.45 mm², and the core power consumption is 27.7 mW at a 1.0-V supply.