65-nm CMOS dual-gate device for Ka-band broadband low-noise amplifier and high-accuracy quadrature voltage-controlled oscillator

Hong Yeh Chang, Chi Hsien Lin, Yu Cheng Liu, Yeh Liang Yeh, Kevin Chen, Szu Hsien Wu

研究成果: 雜誌貢獻期刊論文同行評審

25 引文 斯高帕斯(Scopus)

摘要

Design and analysis of a two-stage low-noise amplifier (LNA) and a bottom-series coupled quadrature voltage-controlled oscillator (QVCO) using a 65-nm CMOS dual-gate device are present in this paper. By using the proposed dual-gate device, the parasitic capacitance and the effective substrate resistance can be reduced. Moreover, the 3-dB cutoff frequency can be extended due to the reduction of the Miller effect. The bandwidth of the dual-gate LNA is investigated to compare with the conventional cascode configuration. Besides, the operation principle of the quadrature signal generation using the dual-gate device is also presented for the QVCO design. The two-stage dual-gate LNA demonstrates a flat 3-dB bandwidth of 7.3 GHz from 19.4 to 26.7 GHz and a maximum gain of 18.9 dB. At 24 GHz, the measured minimum noise figure is 4.7 dB, and the measured output third-order intercept point (OIP3) is 11 dBm. The dual-gate QVCO exhibits an oscillation frequency of up to 25.3 GHz, a phase noise of-109 dBc/Hz at 1-MHz offset frequency, an amplitude error of 0.16 dB, and a phase error of 0.8°. The proposed dual-gate CMOS device is very suitable for the linear and nonlinear circuit designs above 20 GHz, especially for millimeter-wave applications due to its high speed and compact area.

原文???core.languages.en_GB???
文章編號6514132
頁(從 - 到)2402-2413
頁數12
期刊IEEE Transactions on Microwave Theory and Techniques
61
發行號6
DOIs
出版狀態已出版 - 2013

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