64-bit pipeline carry lookahead adder using ALL-N-transistor TSPC logics

Kuo Hsing Cheng, Shun Wen Cheng, Wen Shiuan Lee

研究成果: 雜誌貢獻回顧評介論文同行評審

4 引文 斯高帕斯(Scopus)


This paper proposes two improved circuit techniques of True Single-Phase Clocking (TSPC) logic, which called Nonfull Swing TSPC (NSTSPC) and All-N-TSPC (ANTSPC). The voltage of internal node of the NSTSPC is not full swing; it saves partial dynamic power dissipation. And the ANTSPC uses NMOS transistors to replace PMOS transistors, the output loading of 4-section is therefore reduced and a higher layout density is obtained. Through postlayout simulation comparisons between number of stacked MOS transistors and delay time, and supply voltage vs maximum frequency, the proposed NSTSPC and ANTSPC circuits show better operation speed and power performance than the conventional TSPC circuit. Finally, the new TSPC circuits are applied to a 64-bit hierarchical pipeline Carry Lookahead Adder (CLA), which based on TSMC 0.35 μm CMOS process technology. By using the techniques of NSTSPC and ANTSPC alternately, the 64-bit CLA is successfully implemented as a pipelined structure. The results of post-layout simulation show that the 64-bit CLA can be operated on 1.25GHz clock frequency and its power/maximal frequency ratio is 151.4μW/MHz.

頁(從 - 到)13-27
期刊Journal of Circuits, Systems and Computers
出版狀態已出版 - 2月 2006


深入研究「64-bit pipeline carry lookahead adder using ALL-N-transistor TSPC logics」主題。共同形成了獨特的指紋。