64-Bit hybrid dual-threshold voltage power-aware conditional carry adder design

Kuo Hsing Cheng, Shun Wen Cheng, Chan Wei Huang

研究成果: 書貢獻/報告類型會議論文篇章同行評審

1 引文 斯高帕斯(Scopus)

摘要

A 64-bit hybrid dual-threshold conditional-carry adder for power-aware applications was presented. Components on critical paths use a low threshold voltage to accelerate the speed of operation. Other components use the normal threshold voltage to save power. This is attractive in implementing power-aware arithmetic systems. The proposed circuit has the lowest power-delay product and energy-delay product. The hybrid circuit represents a fine compromise between power and performance. Its power efficiency is better than that of the single threshold voltage circuit designs.

原文???core.languages.en_GB???
主出版物標題Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004
編輯W. Badawy, Y. Ismail
頁面65-68
頁數4
出版狀態已出版 - 2004
事件Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004 - Banff, Alta, Canada
持續時間: 19 7月 200421 7月 2004

出版系列

名字Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004

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???event.eventtypes.event.conference???Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004
國家/地區Canada
城市Banff, Alta
期間19/07/0421/07/04

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