2.1 dB noise figure 5.2 GHz CMOS low noise amplifier using wafer-level integrated passive device technology with a DC power consumption of 10 mW

K. C. Lin, H. K. Chiou, D. C. Chang, Y. Z. Juang

研究成果: 雜誌貢獻期刊論文同行評審

2 引文 斯高帕斯(Scopus)

摘要

This work presents an inductor with a high quality factor (Q) that is fabricated using wafer-level integrated passive device (IPD) technology a 5.2 GHz differential low noise amplifier (DLNA) in a Taiwan semiconductor manufacturing company (TSMC™) 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. The IPD inductors were stacked on top of a CMOS DLNA. The use of IPD inductors in the input matching network (IMN) is an efficient alternative to on-chip inductors for mass production. The performance of the DLNA with without an IPD inductor is studied. The IPD CMOS-DLNA achieves a noise figure (NF) of 2.1 dB with a power consumption of 10 mW. The measured NF of the CMOS-IPD DLNA is 0.6 dB better than that of the typical CMOS DLNA at the same power consumption. The CMOS-IPD DLNA achieves the best figure of merit of any of the recently described 5-6 GHz CMOS LNAs.

原文???core.languages.en_GB???
頁(從 - 到)1286-1290
頁數5
期刊IET Microwaves, Antennas and Propagation
6
發行號11
DOIs
出版狀態已出版 - 21 8月 2012

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