@inproceedings{1c231a7cecb54e12b976720bcff646a9,
title = "1st- Order to 2nd Order Threshold Logic Gate Transformation with an Enhanced IPL-based identification Method",
abstract = "This paper introduces a method to enhance an integer linear programming (ILP)-based method for transforming a 1 -order threshold logic gate (1-TLG) to a 2 -order TLG (2-TLG) with lower area cost. We observe that for a 2-TLG, most of the 2 -order weights (2-weights) are zero. That is, in the ILP formulation, most of the variables for the 2-weights could be set to zero. Thus, we first propose three sufficient conditions for transforming a 1-TLG to a 2-TLG by extracting 2-weights. These extracted weights are seen to be more likely non-zero. Then, we simplify the ILP formulation by eliminating the non-extracted 2-weights to speed up the ILP solving. The experimental results show that, to transform a set of 1-TLGs to 2-TLGs, the enhanced method saves an average of 24% CPU time with only an average of 1.87% quality loss in terms of the area cost reduction rate.",
author = "Zheng, {Li Cheng} and Chang, {Hao Ju} and Chen, {Yung Chih} and Jou, {Jing Yang}",
note = "Publisher Copyright: {\textcopyright} 2021 Association for Computing Machinery.; 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 ; Conference date: 18-01-2021 Through 21-01-2021",
year = "2021",
month = jan,
day = "18",
doi = "10.1145/3394885.3431558",
language = "???core.languages.en_GB???",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "469--474",
booktitle = "Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021",
}