This work describes a CMOS 8 * 8-bit parallel multiplier for 1.2 V supply voltage. The low-power current-sensing complementary pass-transistor logic (LCSCPTL) is applied to the design of the parallel multiplier. The LCSCPTL have certain advantages in both speed and power dissipation over the CPL circuit. The 4-2 compressors and the conditional carry selection scheme are used in this design to achieve regular layout and improve the operation speed. Moreover, the 1.2 V low-voltage 8 * 8-bit parallel multiplier can be designed and fabricated without changing the conventional 5 V 0.8 m CMOS process. Based upon the HSPICE simulation results, the operation speed of the parallel multiplier is 54 ns for 1.2 V supply voltage.
|出版狀態||已出版 - 1996|
|事件||Proceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2) - Rodos, Greece|
持續時間: 13 10月 1996 → 16 10月 1996
|???event.eventtypes.event.conference???||Proceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2)|
|期間||13/10/96 → 16/10/96|