0.5V 160-MHz 260uW all digital phase-locked loop

Jen Chieh Liu; Hong Yi Huang; Wei Bin Yang; Kuo Hsing Cheng

doi:10.1109/DDECS.2009.5012125

0.5V 160-MHz 260uW all digital phase-locked loop

Jen Chieh Liu, Hong Yi Huang, Wei Bin Yang, Kuo Hsing Cheng

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

4 引文斯高帕斯（Scopus）

摘要

A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.

原文	???core.languages.en_GB???
主出版物標題	Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009
頁面	186-189
頁數	4
DOIs	https://doi.org/10.1109/DDECS.2009.5012125
出版狀態	已出版 - 2009
事件	2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009 - Liberec, Czech Republic 持續時間: 15 4月 2009 → 17 4月 2009

出版系列

名字	Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009
國家/地區	Czech Republic
城市	Liberec
期間	15/04/09 → 17/04/09

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10.1109/DDECS.2009.5012125

引用此

Liu, J. C., Huang, H. Y., Yang, W. B., & Cheng, K. H. (2009). 0.5V 160-MHz 260uW all digital phase-locked loop. 於 Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009 (頁 186-189). 文章 5012125 (Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009). https://doi.org/10.1109/DDECS.2009.5012125

@inproceedings{863fd1dde14e4889abfd88509cf1f95d,

title = "0.5V 160-MHz 260uW all digital phase-locked loop",

abstract = "A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.",

author = "Liu, {Jen Chieh} and Huang, {Hong Yi} and Yang, {Wei Bin} and Cheng, {Kuo Hsing}",

year = "2009",

doi = "10.1109/DDECS.2009.5012125",

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isbn = "9781424433391",

series = "Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009",

pages = "186--189",

booktitle = "Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009",

note = "2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009 ; Conference date: 15-04-2009 Through 17-04-2009",

}

Liu, JC, Huang, HY, Yang, WB & Cheng, KH 2009, 0.5V 160-MHz 260uW all digital phase-locked loop. 於 Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009., 5012125, Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, 頁 186-189, 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, Liberec, Czech Republic, 15/04/09. https://doi.org/10.1109/DDECS.2009.5012125

0.5V 160-MHz 260uW all digital phase-locked loop. / Liu, Jen Chieh; Huang, Hong Yi; Yang, Wei Bin 等.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009. 2009. p. 186-189 5012125 (Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

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AU - Cheng, Kuo Hsing

PY - 2009

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N2 - A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.

AB - A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.

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SN - 9781424433391

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Liu JC, Huang HY, Yang WB, Cheng KH. 0.5V 160-MHz 260uW all digital phase-locked loop. 於 Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009. 2009. p. 186-189. 5012125. (Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009). doi: 10.1109/DDECS.2009.5012125

0.5V 160-MHz 260uW all digital phase-locked loop

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