0.5-6 GHz low-voltage low-power mixer using a modified cascode topology in 0.18 μm CMOS technology

K. H. Liang, H. Y. Chang

研究成果: 雜誌貢獻期刊論文同行評審

24 引文 斯高帕斯(Scopus)

摘要

A broadband low-voltage low-power down-conversion mixer using a 0.18 μm standard CMOS process is presented. The proposed mixer uses a modified cascode topology with a bulk-injection technique to achieve low-voltage and low-power performance. The mixer features a maximum conversion gain of 6 dB at a radio frequency (RF) of 2.4 GHz, a single-sideband (SSB) noise figure of 15.2 dB, and an input third-order intercept point (IIP3) of 0 dBm. Moreover, the chip area of the mixer core is only 0.15×0.23 mm2. The measured 3 dB RF bandwidth is from 0.5 to 6 GHz with an intermediate frequency (IF) of 100 MHz. The optimum DC supply voltage (VDD) can be scaled down to 0.7 V with a drain current within 0.4 mA. The supply voltage and DC power of this circuit can be compatible with an advanced 90 or 65 nm CMOS technology.

原文???core.languages.en_GB???
頁(從 - 到)167-174
頁數8
期刊IET Microwaves, Antennas and Propagation
5
發行號2
DOIs
出版狀態已出版 - 31 1月 2011

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