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堆疊式記憶體測試與可靠度增強技術(1/3)
Li, Jin-Fu
(PI)
電機工程學系
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Keyphrases
Stacked Memory
100%
Enhancement Techniques
100%
Reliability Enhancement
100%
3D IC
66%
Reliability Techniques
50%
Design Reliability
33%
Error Correction Codes
33%
Device Reliability
16%
Design Technology
16%
Controller
16%
IC Design
16%
Circuit Reliability
16%
Through Silicon via
16%
Power Ground
16%
Built-in Self-repair
16%
Architectural Level
16%
Dynamic Error Correction
16%
Test Optimization
16%
Memory Array
16%
Repair Method
16%
Built-in-self-test (BiST)
16%
Volume Production
16%
Processor Core
16%
Testability
16%
Effective Testing
16%
Reliability Analysis
16%
Ground Network
16%
Optimization Techniques
16%
Engineering
Correction Code
100%
Design for Reliability
100%
Error Correction
100%
Stack Memory
50%
Processor Core
50%
Integrated Circuit Design
50%
Reliability Analysis
50%
Memory Array
50%
Optimization Technique
50%
Production Volume
50%
Testability
50%
Built-in Self Test
50%
Test Technique
50%
Computer Science
Error Correction Code
100%
Architecture Level
50%
through silicon vias
50%
Controller Level
50%
build-in self-test
50%
Memory Array
50%
Processor Core
50%
Optimization Technique
50%
Technology Design
50%