運算記憶體之測試與可靠性增強技術-總計畫暨子計畫一：運算記憶體之測試策略與自動化技術(3/3)

研究成果

每年研究成果 2023 2023 2023

• 3 會議論文篇章

每年研究成果

每年研究成果

搜尋結果

• 2023

  Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs

  Wu, M. S., Chua, Y. L., Li, J. F., Chuan, Y. T. & Huang, S. H., 2023, Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023. Institute of Electrical and Electronics Engineers Inc., (Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023).

  研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • Spin-transfer Torque Magnetic RAM (STT-MRAM) 100%
  • Read Reliability 100%
  • Fault Aware 100%
  • Error Correction 100%
  • Error Correction Code 100%
  2 引文 斯高帕斯（Scopus）

• Hardware Trojans of Computing-In-Memories: Issues and Methods

  Huang, S. H., Cheng, W. C. & Li, J. F., 2023, 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Cassano, L., Psarakis, M., Traiola, M. & Bosio, A. (編輯). Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

  研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • In-memory 100%
  • Hardware Trojan 100%
  • Computer Hardware 100%
  • Security Design 40%
  • Data Storage 20%

• Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability

  Li, J. F., 2023, 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Cassano, L., Psarakis, M., Traiola, M. & Bosio, A. (編輯). Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

  研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • Testing Algorithm 100%
  • Memory Faults 100%
  • Test Design 100%
  • Design for Testability 100%
  • Fault Test 100%
  1 引文 斯高帕斯（Scopus）