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查看斯高帕斯 (Scopus) 概要
陳 聿廣
助理教授
電機工程學系
電子郵件
andyygchen
ee.ncu.edu
tw
網站
https://cis.ncu.edu.tw/iTeacher/home/0x6e74225a3a58e4df9ccfbf5f831c935a
h-index
117
引文
6
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
2011
2025
每年研究成果
概覽
指紋
網路
研究計畫
(9)
研究成果
(38)
類似的個人檔案
(6)
指紋
查看啟用 Yu-Guang Chen 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Keyphrases
3D IC
41%
Aging
38%
Aging Effect
23%
Aging Monitoring
12%
Aging Resilience
12%
Aging-aware
17%
Algorithm Design
12%
Area Overhead
50%
Asymmetric Aging
14%
CAD Contest
19%
Concept Design
25%
Convolutional Neural Network
16%
Cost Dynamics
12%
Design Concept
25%
Dynamic Voltage Scaling
26%
Edge Devices
16%
Electronic Design Automation
19%
Energy Efficient
19%
Fault Tolerance Mechanism
17%
Graceful Degradation
25%
High Performance
15%
IC Recycling
12%
Increased Reliability
19%
Industrial Design
14%
IR Drop
15%
Leakage Power
26%
Low Power Optimization
12%
Machine Learning
14%
Mode Transition
16%
Multi-bit
16%
Multicore Systems
25%
NbTi
12%
Negative Bias Temperature Instability
65%
Online Module
12%
PMOS
21%
Power Consumption
17%
Power Gating
13%
Reliability Issues
18%
Retention Register
25%
Scaling Scheme
13%
Sleep Transistor
21%
Smart Devices
12%
System Lifetime
15%
Through Silicon via
25%
Time Constraints
29%
Timing Error
15%
Timing Failures
13%
Transition Detector
12%
Wake-up
38%
Yield Constraints
21%
Computer Science
Clock Cycle
8%
Compressed Sensing
12%
Computer Aided Design
19%
Computer Hardware
7%
Convolutional Neural Network
28%
Critical Path
12%
Depthwise Separable Convolution
8%
Design Procedure
8%
Detection Method
8%
Dynamic Power
12%
Dynamic Voltage
10%
Dynamic Voltage Scaling
28%
Electronic Design Automation
19%
Enabling Technique
8%
Energy Efficient
6%
Experimental Result
100%
Fault Tolerance Mechanism
17%
Global Routing
12%
Graceful Degradation
25%
Integrated Circuit
20%
Internet-Of-Things
12%
Learning System
19%
Machine Learning
19%
Multicore System
32%
Neural Network
15%
Optimal Assignment
8%
Parallelism
12%
Physical Design
14%
Power Consumption
38%
Power Distribution Network
12%
Power Efficiency
12%
Power Efficient
8%
Power Optimization
12%
Prediction Framework
12%
Preventive Maintenance
12%
Process Variation
9%
Product Design
18%
Reconfigurable Logic
12%
Reconfiguration
17%
Signal Integrity
17%
Sleep Transistor
51%
Smart Device
12%
Speed-up
8%
Supply Voltage
8%
Task Parallelism
12%
Threshold Voltage
17%
through silicon vias
25%
Timing Constraint
28%
Training Sample
11%
Transition Mode
12%
Engineering
Aging Effect
8%
Area Overhead
29%
Clock Cycle
19%
Compressed Sensing
12%
Concept Design
12%
Control Vector
6%
Convolutional Neural Network
6%
Data Store
12%
Design Concept
25%
Design Constraint
12%
Design Element
6%
Design Factor
6%
Design for Reliability
12%
Design Function
6%
Design Stage
6%
Electric Power Distribution
12%
Energy Engineering
12%
Excessive Leakage
6%
Experimental Result
43%
Fits and Tolerances
20%
Gate Oxide
6%
Input Vector
6%
Integrated Circuit Design
6%
Internal Node
6%
Internet-Of-Things
12%
Learning System
12%
Magnetic Tunnel Junction
6%
Negative-Bias Temperature Instability
19%
Noise Margin
6%
Performance Degradation
6%
Power Distribution
12%
Preventive Maintenance
12%
Processing Element
6%
Product Design
9%
Prototype
6%
Reliability Issue
14%
Sensor Noise
6%
Single Bit
12%
Sleep Mode
25%
Space Solution
6%
Storage Area
6%
Storage Size
25%
Supply Voltage
14%
Switching Activity
6%
System-on-Chip
12%
Three Dimensional Integrated Circuits
12%
Voltage Regulator
12%
