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查看斯高帕斯 (Scopus) 概要
陳 聿廣
副教授
電機工程學系
電子郵件
andyygchen
ee.ncu.edu
tw
網站
https://cis.ncu.edu.tw/iTeacher/home/0x6e74225a3a58e4df9ccfbf5f831c935a
h-index
127
引文
6
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
2011
2025
每年研究成果
概覽
指紋
網路
研究計畫
(9)
研究成果
(41)
類似的個人檔案
(6)
指紋
查看啟用 Yu-Guang Chen 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Keyphrases
Negative Bias Temperature Instability
64%
Area Overhead
49%
3D IC
40%
Wake-up
37%
Aging
37%
Time Constraints
28%
Leakage Power
26%
Dynamic Voltage Scaling
26%
Graceful Degradation
25%
Through Silicon via
25%
Retention Register
25%
Concept Design
25%
Design Concept
25%
Multicore Systems
25%
Aging Effect
22%
Sleep Transistor
21%
Yield Constraints
21%
PMOS
20%
CAD Contest
18%
Energy Efficient
18%
Increased Reliability
18%
Electronic Design Automation
18%
Reliability Issues
18%
Power Consumption
17%
Fault Tolerance Mechanism
16%
Aging-aware
16%
Mode Transition
15%
Multi-bit
15%
Edge Devices
15%
Convolutional Neural Network
15%
IR Drop
15%
System Lifetime
15%
High Performance
15%
Timing Error
14%
Asymmetric Aging
13%
Machine Learning
13%
Industrial Design
13%
Power Gating
13%
Scaling Scheme
13%
Timing Failures
13%
Aging Monitoring
12%
Transition Detector
12%
Aging Resilience
12%
Low Power Optimization
12%
Cost Dynamics
12%
NbTi
12%
Algorithm Design
12%
Online Module
12%
IC Recycling
12%
Smart Devices
12%
Computer Science
Experimental Result
100%
Sleep Transistor
50%
Power Consumption
37%
Multicore System
31%
Timing Constraint
28%
Convolutional Neural Network
27%
Dynamic Voltage Scaling
27%
through silicon vias
25%
Graceful Degradation
25%
Integrated Circuit
20%
Electronic Design Automation
18%
Machine Learning
18%
Learning System
18%
Computer Aided Design
18%
Product Design
17%
Fault Tolerance Mechanism
16%
Reconfiguration
16%
Signal Integrity
16%
Threshold Voltage
16%
Neural Network
14%
Physical Design
14%
Parallelism
13%
Dynamic Power
13%
Reconfigurable Logic
12%
Power Distribution Network
12%
Smart Device
12%
Task Parallelism
12%
Compressed Sensing
12%
Critical Path
12%
Prediction Framework
12%
Power Optimization
12%
Preventive Maintenance
12%
Transition Mode
12%
Global Routing
12%
Power Efficiency
12%
Internet-Of-Things
12%
Training Sample
11%
Dynamic Voltage
10%
Process Variation
9%
Memory Architecture
9%
Clock Cycle
8%
Design Procedure
8%
Power Efficient
8%
Detection Method
8%
Speed-up
8%
Optimal Assignment
8%
Enabling Technique
8%
Supply Voltage
7%
Depthwise Separable Convolution
7%
Computer Hardware
7%
Engineering
Experimental Result
43%
Area Overhead
28%
Storage Size
25%
Design Concept
25%
Sleep Mode
25%
Negative-Bias Temperature Instability
19%
Fits and Tolerances
19%
Clock Cycle
18%
Reliability Issue
14%
Supply Voltage
14%
Design for Reliability
12%
Three Dimensional Integrated Circuits
12%
Electric Power Distribution
12%
Power Distribution
12%
Energy Engineering
12%
Data Store
12%
System-on-Chip
12%
Single Bit
12%
Compressed Sensing
12%
Preventive Maintenance
12%
Concept Design
12%
Voltage Regulator
12%
Design Constraint
12%
Learning System
12%
Internet-Of-Things
12%
Aging Effect
10%
Product Design
9%
Convolutional Neural Network
7%
Noise Margin
6%
Input Vector
6%
Control Vector
6%
Sensor Noise
6%
Performance Degradation
6%
Switching Activity
6%
Storage Area
6%
Internal Node
6%
Magnetic Tunnel Junction
6%
Gate Oxide
6%
Integrated Circuit Design
6%
Design Factor
6%
Space Solution
6%
Design Stage
6%
Excessive Leakage
6%
Design Element
6%
Design Function
6%
Prototype
6%
Processing Element
6%
Systolic Arrays
6%
