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查看斯高帕斯 (Scopus) 概要
陳 聿廣
副教授
電機工程學系
電子郵件
andyygchen
ee.ncu.edu
tw
網站
https://cis.ncu.edu.tw/iTeacher/home/0x6e74225a3a58e4df9ccfbf5f831c935a
h-index
171
引文
7
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
2011
2025
每年研究成果
概覽
指紋
網路
研究計畫
(9)
研究成果
(52)
類似的個人檔案
(1)
指紋
查看啟用 Yu-Guang Chen 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Keyphrases
Negative Bias Temperature Instability
62%
Area Overhead
46%
3D IC
38%
Aging
36%
Wake-up
36%
Time Constraints
27%
Leakage Power
26%
Dynamic Voltage Scaling
24%
Aging Effect
24%
Graceful Degradation
24%
Through Silicon via
24%
Retention Register
24%
Concept Design
24%
Design Concept
24%
Multicore Systems
24%
Increased Reliability
24%
Deep Neural Network
24%
Sleep Transistor
20%
Yield Constraints
20%
PMOS
19%
CAD Contest
18%
Energy Efficient
18%
Electronic Design Automation
18%
Aging-aware
17%
Reliability Issues
17%
Power Consumption
16%
Fault Tolerance Mechanism
16%
Timing Error
15%
Mode Transition
15%
Multi-bit
15%
Edge Devices
15%
Convolutional Neural Network
15%
IR Drop
14%
System Lifetime
14%
High Performance
14%
Processing-In-Memory Architectures
14%
Asymmetric Aging
13%
Machine Learning
13%
Industrial Design
13%
Power Gating
12%
Scaling Scheme
12%
Timing Failures
12%
Aging Monitoring
12%
Transition Detector
12%
Aging Resilience
12%
Low Power Optimization
12%
Cost Dynamics
12%
NbTi
12%
Algorithm Design
12%
Online Module
12%
Computer Science
Experimental Result
100%
Sleep Transistor
48%
Convolutional Neural Network
36%
Power Consumption
35%
Multicore System
30%
Deep Neural Network
30%
Timing Constraint
26%
Dynamic Voltage Scaling
26%
through silicon vias
24%
Graceful Degradation
24%
Neural Network
23%
Memory Architecture
21%
Integrated Circuit
20%
Physical Design
19%
Electronic Design Automation
18%
Machine Learning
18%
Learning System
18%
Computer Aided Design
18%
Product Design
17%
Fault Tolerance Mechanism
16%
Reconfiguration
16%
Signal Integrity
16%
Threshold Voltage
16%
Neural Network Model
15%
Power Efficiency
15%
Global Routing
15%
Parallelism
14%
Dynamic Power
14%
Reconfigurable Logic
12%
Power Distribution Network
12%
Smart Device
12%
Task Parallelism
12%
Compressed Sensing
12%
Critical Path
12%
Prediction Framework
12%
Power Optimization
12%
Preventive Maintenance
12%
Transition Mode
12%
Internet-Of-Things
12%
Training Sample
11%
Dynamic Voltage
9%
Process Variation
9%
Training Data
9%
Clock Cycle
8%
Design Procedure
8%
Power Efficient
8%
Detection Method
8%
Speed-up
8%
Optimal Assignment
8%
Enabling Technique
8%
Engineering
Experimental Result
42%
Area Overhead
26%
Storage Size
24%
Design Concept
24%
Sleep Mode
24%
Negative-Bias Temperature Instability
18%
Fits and Tolerances
18%
Clock Cycle
18%
Reliability Issue
13%
Supply Voltage
13%
Convolutional Neural Network
13%
Design for Reliability
12%
Three Dimensional Integrated Circuits
12%
Electric Power Distribution
12%
Power Distribution
12%
Data Store
12%
System-on-Chip
12%
Single Bit
12%
Compressed Sensing
12%
Preventive Maintenance
12%
Concept Design
12%
Voltage Regulator
12%
Design Constraint
12%
Learning System
12%
Internet-Of-Things
12%
Molybdenum Disulfide
12%
Field Effect Transistor
12%
Integrated Circuit Design
12%
Deep Neural Network
12%
Aging Effect
10%
Product Design
9%
Design Stage
9%
Image Processing
6%
Noise Margin
6%
Input Vector
6%
Control Vector
6%
Sensor Noise
6%
Performance Degradation
6%
Switching Activity
6%
Storage Area
6%
Internal Node
6%
Magnetic Tunnel Junction
6%
Gate Oxide
6%
Design Factor
6%
Space Solution
6%
Excessive Leakage
6%
Design Element
6%
Design Function
6%
Processing Element
6%
Systolic Arrays
6%
